Merge boneless_sim with Boneless-CPU #1

cr1901 · 2018-12-25T06:40:40Z

Exactly what it says on the tin.

setup.py working properly on my mind (both boneless and boneless_sim packages installed).
Tests are properly discovered for both boneless and boneless_sim. The simulator tests pass on my end. The gateware tests on my machine fail with errors of the following form:

ERROR: test_XOR (boneless.gateware.test_core.BonelessTestCase)
----------------------------------------------------------------------
Traceback (most recent call last):
 File "C:\msys64\home\William\src\boneless-sim\boneless\gateware\test_core.py", line 14, in wrapper
   run_simulation(self.tb, case(self, self.tb), vcd_name="test.vcd")
 File "C:\msys64\home\william\src\nmigen\nmigen\compat\sim\__init__.py", line 19, in run_simulation
   with Simulator(fragment, vcd_file=open(vcd_name, "w") if vcd_name else None) as sim:
 File "C:\msys64\home\william\src\nmigen\nmigen\back\pysim.py", line 505, in __enter__
   var_type=var_type, size=var_size, init=var_init))
 File "C:\msys64\mingw64\lib\python3.6\site-packages\pyvcd-0.1.3-py3.6.egg\vcd\writer.py", line 144, in register_var
   raise ValueError('Invalid var_type "{}"'.format(var_type))
ValueError: Invalid var_type "string"

Badges have been updated to point to your accounts.
.travis.yml, readthedocs.yml unmodified, ready for your changes.
.gitignore, setup.py merged.
Stub README.md added. It is included by the top-level docs. I want to share the docs between boneless and boneless_sim.

:100644 100644 159aa0c 6dbb54a M boneless_sim/test/test_insns.py :100644 100644 159aa0c 6dbb54a M boneless_sim/test/test_insns.py

:100644 100644 e33125a e81849b M boneless_sim/sim.py

:100644 100644 03b1a8d a2b6146 M boneless_sim/sim.py :100644 100644 30a21a9 98cde93 M boneless_sim/test/test_insns.py

:000000 100644 0000000 dc34c84 A .travis.yml :000000 100644 0000000 05f18df A README.md :000000 100644 0000000 a4b0039 A .travis.yml :000000 100644 0000000 05f18df A README.md :000000 100644 0000000 a4b0039 A .travis.yml :000000 100644 0000000 a653b47 A README.md :000000 100644 0000000 f7cefe6 A .travis.yml :000000 100644 0000000 adf06b7 A README.md :000000 100644 0000000 e093d10 A .travis.yml :000000 100644 0000000 adf06b7 A README.md :000000 100644 0000000 6178ee4 A .travis.yml :000000 100644 0000000 adf06b7 A README.md

:000000 100644 0000000 0a19fdb A .readthedocs.yml :100644 100644 adf06b7 793bddd M README.md :000000 100644 0000000 5ea5b22 A .readthedocs.yml :100644 100644 adf06b7 793bddd M README.md

:100644 100644 7504957 29a8fa3 M boneless_sim/sim.py

whitequark · 2018-12-25T06:56:41Z

Tests are properly discovered for both boneless and boneless_sim. The simulator tests pass on my end. The gateware tests on my machine fail with errors of the following form:

You need pyvcd>=0.1.4. This is in nmigen's dependencies, actually, not sure why it doesn't work.

whitequark · 2018-12-25T06:57:43Z

setup.py working properly on my mind (both boneless and boneless_sim packages installed).

The package should be called boneless.simulator, similar to boneless.gateware.

:100644 100644 a378e36 4fa19b7 M boneless/simulator/sim.py

…ag attributes.

…lude argument.

:100644 100644 7ca3470 021514d M .travis.yml

codecov-io · 2018-12-26T09:30:14Z

Codecov Report

❗ No coverage uploaded for pull request base (master@32debb8). Click here to learn what that means.
The diff coverage is 99.43%.

@@            Coverage Diff            @@
##             master       #1   +/-   ##
=========================================
  Coverage          ?   96.34%           
=========================================
  Files             ?       13           
  Lines             ?     1257           
  Branches          ?        0           
=========================================
  Hits              ?     1211           
  Misses            ?       46           
  Partials          ?        0

Impacted Files	Coverage Δ
boneless/simulator/__init__.py	`100% <100%> (ø)`
boneless/simulator/test/test_insns.py	`100% <100%> (ø)`
boneless/simulator/test/test_idioms.py	`100% <100%> (ø)`
boneless/simulator/test/common.py	`96.29% <96.29%> (ø)`
boneless/simulator/test/test_except.py	`97.61% <97.61%> (ø)`
boneless/simulator/sim.py	`99.56% <99.56%> (ø)`

Continue to review full report at Codecov.

Legend - Click here to learn more
Δ = absolute <relative> (impact), ø = not affected, ? = missing data
Powered by Codecov. Last update 32debb8...dfb7255. Read the comment docs.

cr1901 · 2019-03-09T17:38:35Z

@whitequark Boneless Arch is finalized, correct? In the upcoming week, I plan to modify the simulator so it has feature parity w/ the arch itself.

And maybe add async support. Idk how much good it'll do, since a CPU arch simulator doesn't have to wait for anything when simulating ALU/mem ops. But maybe it might be useful to schedule opcodes in the event loop between, say, simulated I/O peripherals. Thoughts?

whitequark · 2019-03-09T18:58:22Z

Boneless Arch is finalized, correct? In the upcoming week, I plan to modify the simulator so it has feature parity w/ the arch itself.

Not yet.

cr1901 added 30 commits December 4, 2018 05:08

Initial commit.

4aa3733

Implement Class A insns and test.

cf3ad3a

Refactor sim into more functions, slightly clean up tests.

dc7a104

Fix MOVH instruction.

6987c9d

Implement MOVA insn.

b81cdcc

Implement ADDI/SUBI insn.

37da130

Implement LDI/STI insns.

053ccdd

Implement JAL/JR insns, Class I implemented.

8ddc5b4

Fix MOVL/MOVH semantics and tests.

348397e

Implement S-class insns (untested).

98da4cb

Refactor tests (one test currently does not pass).

e9f471b

Rework flags semantics for ADD/SUB.

acb6654

Rework ADDI/SUBI flag semantics.

581463c

Slight cleanup, add stub tests for remaining insn classes.

2a4bf0a

:100644 100644 159aa0c 6dbb54a M boneless_sim/test/test_insns.py :100644 100644 159aa0c 6dbb54a M boneless_sim/test/test_insns.py

Implement tests for/fix S-class insns.

3369779

Refactor out flag functions.

a3f749f

:100644 100644 e33125a e81849b M boneless_sim/sim.py

Add M-class insns and tests.

bc13bbf

Implement C-class insns, start adding tests.

f04e40b

Remove errant print functions.

b0b4254

Add CMP tests and improve CMP/SUB implementation.

d3d5b3c

:100644 100644 03b1a8d a2b6146 M boneless_sim/sim.py :100644 100644 30a21a9 98cde93 M boneless_sim/test/test_insns.py

Fixed swapped operands to CMP in test_jmps.

c3c1830

Fill out setup.py.

c2d660f

Add Sphinx documentation.

5d3dfb3

Add proper documentation for register_io, choose docs theme.

1e71467

Add ReadtheDocs Support.

63a7475

:000000 100644 0000000 0a19fdb A .readthedocs.yml :100644 100644 adf06b7 793bddd M README.md :000000 100644 0000000 5ea5b22 A .readthedocs.yml :100644 100644 adf06b7 793bddd M README.md

Add class and regs documentation.

1c93ecb

Quiet down travis notifications.

285529a

Add remaining documentation for public members.

572d243

:100644 100644 7504957 29a8fa3 M boneless_sim/sim.py

Make insn class handling methods private.

bffd485

cr1901 added 12 commits December 10, 2018 05:46

Add remaining C-class tests to improve coverage; some tests fail.

de2ea52

Add 32-bit subtraction test, fix ADDI flags.

e55234a

Use 0-clause BSD License.

148f54d

Add custom 0BSD license badge, since Github doesn't support it.

346e44f

Modify CMP to reflect changed semantics (CMP B, A => CMP A, B).

0727f3b

Fix jumps according to updated spec.

1d1e822

Correct JMP tests affected by swapped CMP operands.

ba910bb

Create BonelessError exception.

b601e0d

Add tests for exceptions and sim_active conditions.

e85af4c

Attempt to get 100% coverage.

20d353a

Add BonelessError to docs.

77a02ae

Merge unrelated repo boneless_sim into boneless.

9f98dae

cr1901 added 9 commits December 25, 2018 02:04

Remove redundant LICENSE.md file.

a029ef6

Move boneless_sim => boneless.simulator, update docs accordingly.

9d8f92c

.travis.yml: Remove outdated build steps.

168b327

simulator.sim: Remove references to Glasgow in docs.

bf2d5c1

simulator.sim: Fix typos, memsize => mem_size, 16 => 8.

af0614e

:100644 100644 a378e36 4fa19b7 M boneless/simulator/sim.py

boneless.simulator: Remove flags dictionary in favor of individual fl…

8dc71fe

…ag attributes.

simulator.sim: Remove redundant BonelessException constructor.

6d05751

setup.py: Remove nonexistent tests directory from find_packages() exc…

0ac163a

…lude argument.

travis.yml: Make sure to download nmigen.

2957b55

:100644 100644 7ca3470 021514d M .travis.yml

cr1901 added 2 commits December 26, 2018 04:48

boneless.simulator: Use relative imports.

db2b246

README.md: Update badge URLs.

dfb7255

cr1901 mentioned this pull request Mar 9, 2019

Assembler cr1901/boneless-sim#1

Closed

whitequark force-pushed the master branch from 8ba7240 to c6f00b2 Compare August 24, 2019 22:45

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Merge boneless_sim with Boneless-CPU #1

Merge boneless_sim with Boneless-CPU #1

cr1901 commented Dec 25, 2018

whitequark commented Dec 25, 2018

whitequark commented Dec 25, 2018 •

edited

codecov-io commented Dec 26, 2018 •

edited

cr1901 commented Mar 9, 2019

whitequark commented Mar 9, 2019

Merge boneless_sim with Boneless-CPU #1

Are you sure you want to change the base?

Merge boneless_sim with Boneless-CPU #1

Conversation

cr1901 commented Dec 25, 2018

whitequark commented Dec 25, 2018

whitequark commented Dec 25, 2018 • edited

codecov-io commented Dec 26, 2018 • edited

Codecov Report

cr1901 commented Mar 9, 2019

whitequark commented Mar 9, 2019

whitequark commented Dec 25, 2018 •

edited

codecov-io commented Dec 26, 2018 •

edited