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base repository: whitequark/Boneless-CPU
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head repository: whitequark/Boneless-CPU
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compare: cb79d607fb55
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Dec 24, 2018

  1. Minor clarify fixes.

    @whitequark
    whitequark committed Dec 24, 2018
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    bc3945b View commit details

  2. Simplify ALU instruction decoding (-4 LUT).

    @whitequark
    whitequark committed Dec 24, 2018
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    cb79d60 View commit details
Showing with 8 additions and 10 deletions.
  1. +8 −10 boneless/gateware.py
18 changes: 8 additions & 10 deletions boneless/gateware.py
View file
Original file line number Diff line number Diff line change
@@ -71,8 +71,8 @@ def __init__(self, width):

###

# The following mux tree is optimized for 4-LUTs, and fits into the optimal 48 4-LUTs
# on iCE40 using synth_ice40.
# The following mux tree is optimized for 4-LUTs, and fits into the optimal 32 4-LUTs
# and 16 DFFs on iCE40 using synth_ice40.
s_l = Signal(width)
s_r = Signal(width)
s_i1 = Signal(width)
@@ -212,18 +212,16 @@ def decode(v):
self.comb += mem_re.eq(1)

self.submodules.fsm = FSM(reset_state="FETCH")
self.comb += [
s_insn.eq(Mux(self.fsm.ongoing("DECODE/LOAD/JUMP"), mem_r_d, r_insn)),
]
self.fsm.act("FETCH",
mem_r_a.eq(r_pc),
NextValue(r_pc, r_pc + 1),
NextState("DECODE/LOAD/JUMP")
)
self.comb += s_insn.eq(Mux(self.fsm.ongoing("DECODE/LOAD/JUMP"), mem_r_d, r_insn))
self.fsm.act("DECODE/LOAD/JUMP",
NextValue(r_insn, mem_r_d),
If(i_clsA,
mem_r_a.eq(Cat(i_regX, r_win)),
mem_r_a.eq(Cat(i_regY, r_win)),
NextState("A-READ")
).Elif(i_clsS,
mem_r_a.eq(Cat(i_regY, r_win)),
@@ -258,12 +256,12 @@ def decode(v):
)
)
self.fsm.act("A-READ",
mem_r_a.eq(Cat(i_regY, r_win)),
NextValue(s_opB, mem_r_d),
mem_r_a.eq(Cat(i_regX, r_win)),
NextValue(r_opA, mem_r_d),
NextState("A-EXECUTE")
)
self.fsm.act("A-EXECUTE",
r_opA.eq(mem_r_d),
s_opB.eq(mem_r_d),
s_res.eq(alu.s_o),
mem_w_a.eq(Cat(i_regZ, r_win)),
mem_w_d.eq(s_res),
@@ -841,7 +839,7 @@ def __init__(self, has_pins=False):
if __name__ == "__main__":
parser = argparse.ArgumentParser()
parser.add_argument(
"type", metavar="TYPE", choices=["alu", "sru", "bus", "pins"], default="bus")
"type", choices=["alu", "sru", "bus", "pins"], default="bus")
cli.main_parser(parser)

args = parser.parse_args()