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base repository: whitequark/Boneless-CPU
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base: f4c05045b609
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head repository: whitequark/Boneless-CPU
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compare: d81a52cf02bf
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  • 1 commit
  • 5 files changed
  • 1 contributor

Commits on Dec 24, 2018

  1. Copy the full SHA
    d81a52c View commit details
Showing with 30 additions and 1 deletion.
  1. +3 −1 boneless/gateware/core_fsm.py
  2. +3 −0 examples/.gitignore
  3. +5 −0 examples/iceblink.pcf
  4. +11 −0 examples/iceblink.sv
  5. +8 −0 examples/run.sh
4 changes: 3 additions & 1 deletion boneless/gateware/core_fsm.py
Original file line number Diff line number Diff line change
@@ -435,11 +435,13 @@ def __init__(self, has_pins=False):
self.mem.init = [
0, 0, 0, 0, 0, 0, 0, 0,
*assemble([
NOP (),
NOP (),
MOVL(R1, 1),
"loop",
STX (R1, R0, 0),
ROT (R1, R1, 1),
MOVH(R2, 1),
MOVH(R2, 80),
"delay",
SUBI(R2, 1),
JNZ ("delay"),
3 changes: 3 additions & 0 deletions examples/.gitignore
Original file line number Diff line number Diff line change
@@ -0,0 +1,3 @@
*.json
*.txt
*.bin
5 changes: 5 additions & 0 deletions examples/iceblink.pcf
Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
set_io clk 13
set_io led[0] 59
set_io led[1] 56
set_io led[2] 53
set_io led[3] 51
11 changes: 11 additions & 0 deletions examples/iceblink.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
module top(...);
input clk;
output [3:0] led;

boneless cpu(
.clk(clk),
.rst(0),
.r_win(0),
.pins(led),
);
endmodule
8 changes: 8 additions & 0 deletions examples/run.sh
Original file line number Diff line number Diff line change
@@ -0,0 +1,8 @@
#!/bin/sh -ex

cd $(dirname $0)
python3 -W ignore -m boneless.gateware.core_fsm pins generate fsm_core_pins.v
yosys fsm_core_pins.v iceblink.sv -p "synth_ice40 -top top -json iceblink.json"
nextpnr-ice40 --hx1k --package vq100 --pcf iceblink.pcf --json iceblink.json --asc iceblink.txt
icepack iceblink.txt iceblink.bin
iCEburn -e -w iceblink.bin