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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 010ddb96b5c0
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Dec 24, 2018

  1. back.rtlil: unbreak d47c1f8.

    whitequark committed Dec 24, 2018
    Copy the full SHA
    010ddb9 View commit details
Showing with 3 additions and 2 deletions.
  1. +3 −2 nmigen/back/rtlil.py
5 changes: 3 additions & 2 deletions nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -644,7 +644,7 @@ def convert_fragment(builder, fragment, name, top):
memories[memory] = module.memory(width=memory.width, size=memory.depth,
name=memory.name)
addr_bits = bits_for(memory.depth)
data_parts = ["{}'".format(memory.width * memory.depth)]
data_parts = []
for addr in range(memory.depth):
if addr < len(memory.init):
data = memory.init[addr]
@@ -653,7 +653,8 @@ def convert_fragment(builder, fragment, name, top):
data_parts.append("{:0{}b}".format(data, memory.width))
module.cell("$meminit", ports={
"\\ADDR": rhs_compiler(ast.Const(0, addr_bits)),
"\\DATA": "".join(data_parts),
"\\DATA": "{}'".format(memory.width * memory.depth) +
"".join(reversed(data_parts)),
}, params={
"MEMID": memories[memory],
"ABITS": addr_bits,