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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: f05bd2a137e6
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Dec 24, 2018

  1. back.rtlil: use one $meminit cell, not one per word.

    This is *far* more efficient.
    whitequark committed Dec 24, 2018
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    d47c1f8 View commit details
  2. hdl.mem: allow omitting memory simulation logic.

    Trying to transform very large arrays is slow.
    whitequark committed Dec 24, 2018

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    This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
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    f05bd2a View commit details
Showing with 17 additions and 14 deletions.
  1. +12 −10 nmigen/back/rtlil.py
  2. +5 −4 nmigen/hdl/mem.py
22 changes: 12 additions & 10 deletions nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -644,21 +644,23 @@ def convert_fragment(builder, fragment, name, top):
memories[memory] = module.memory(width=memory.width, size=memory.depth,
name=memory.name)
addr_bits = bits_for(memory.depth)
data_parts = ["{}'".format(memory.width * memory.depth)]
for addr in range(memory.depth):
if addr < len(memory.init):
data = memory.init[addr]
else:
data = 0
module.cell("$meminit", ports={
"\\ADDR": rhs_compiler(ast.Const(addr, addr_bits)),
"\\DATA": rhs_compiler(ast.Const(data, memory.width)),
}, params={
"MEMID": memories[memory],
"ABITS": addr_bits,
"WIDTH": memory.width,
"WORDS": 1,
"PRIORITY": 0,
})
data_parts.append("{:0{}b}".format(data, memory.width))
module.cell("$meminit", ports={
"\\ADDR": rhs_compiler(ast.Const(0, addr_bits)),
"\\DATA": "".join(data_parts),
}, params={
"MEMID": memories[memory],
"ABITS": addr_bits,
"WIDTH": memory.width,
"WORDS": memory.depth,
"PRIORITY": 0,
})

param_value = memories[memory]

9 changes: 5 additions & 4 deletions nmigen/hdl/mem.py
Original file line number Diff line number Diff line change
@@ -6,7 +6,7 @@


class Memory:
def __init__(self, width, depth, init=None, name=None):
def __init__(self, width, depth, init=None, name=None, simulate=True):
if not isinstance(width, int) or width < 0:
raise TypeError("Memory width must be a non-negative integer, not '{!r}'"
.format(width))
@@ -29,8 +29,9 @@ def __init__(self, width, depth, init=None, name=None):

# Array of signals for simulation.
self._array = Array()
for addr in range(self.depth):
self._array.append(Signal(self.width, name="{}({})".format(name, addr)))
if simulate:
for addr in range(self.depth):
self._array.append(Signal(self.width, name="{}({})".format(name, addr)))

self.init = init

@@ -45,7 +46,7 @@ def init(self, new_init):
raise ValueError("Memory initialization value count exceed memory depth ({} > {})"
.format(len(self.init), self.depth))

for addr in range(self.depth):
for addr in range(len(self._array)):
if addr < len(self._init):
self._array[addr].reset = self._init[addr]
else: