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base repository: whitequark/Boneless-CPU
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head repository: whitequark/Boneless-CPU
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compare: 0fc6d57aa892
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  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Dec 24, 2018

  1. Add XCHG pseudo, expanding to XOR swap.

    @whitequark
    whitequark committed Dec 24, 2018
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    a6a4b36 View commit details

  2. Change the pins test to use PWM.

    @whitequark
    whitequark committed Dec 24, 2018
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    0fc6d57 View commit details
Showing with 31 additions and 5 deletions.
  1. +3 −0 boneless/__init__.py
  2. +23 −4 boneless/gateware/core_fsm.py
  3. +5 −1 boneless/instr.py
3 changes: 3 additions & 0 deletions boneless/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -133,6 +133,9 @@
# Mnemonic: MOV Rd, Ra (alias)
# Operation: Rd ← Ra
#
# Mnemonic: XCHG Rx, Ry (pseudo)
# Operation: {Rx, Ry} ← {Ry, Rx}
#
# Mnemonic: MOVL Rd, imm
# Operation: Rd[15:8] ← 0, Rd[7:0] ← imm
#
27 changes: 23 additions & 4 deletions boneless/gateware/core_fsm.py
View file
Original file line number Diff line number Diff line change
@@ -437,14 +437,33 @@ def __init__(self, has_pins=False):
*assemble([
NOP (),
NOP (),
"init",
MOVL(R1, 1),
"loop",
STX (R1, R0, 0),
ROT (R1, R1, 1),
MOVH(R2, 80),
"delay",
MOVL(R7, 0b10000),
CMP (R1, R7),
JE ("init"),
MOVH(R2, 255),
"breathe",
SRL (R3, R2, 8),
MOVL(R7, 0xff),
AND (R4, R2, R7),
MOVH(R7, 0x80),
AND (R7, R7, R2),
JNZ ("pwm"),
XCHG(R3, R4),
"pwm",
CMP (R3, R4),
JULT("pwmon"),
"pwmoff",
STX (R0, R0, 0),
J ("pwmdone"),
"pwmon",
STX (R1, R0, 0),
"pwmdone",
SUBI(R2, 1),
JNZ ("delay"),
JNZ ("breathe"),
J ("loop"),
])
]
6 changes: 5 additions & 1 deletion boneless/instr.py
View file
Original file line number Diff line number Diff line change
@@ -8,7 +8,7 @@
"ADD", "ADDI", "AND", "CMP", "ILL", "J", "JAL", "JC", "JE", "JNC", "JNE", "JNO", "JNS", "JNZ",
"JO", "JR", "JS", "JSGE", "JSGT", "JSLE", "JSLT", "JUGE", "JUGT", "JULE", "JULT", "JZ",
"LD", "LDI", "LDX", "MOV", "MOVA", "MOVH", "MOVI", "MOVL", "NOP", "OR", "ROT", "ROL", "ROR",
"SLL", "SRA", "SRL", "ST", "STI", "STX", "SUB", "SUBI", "XOR",
"SLL", "SRA", "SRL", "ST", "STI", "STX", "SUB", "SUBI", "XCHG", "XOR",
"L", "assemble",
]

@@ -66,6 +66,10 @@ def AND (rd, ra, rb): return [A_FORMAT(OPCODE_LOGIC, OPTYPE_AND, rd, ra, rb)]
def OR (rd, ra, rb): return [A_FORMAT(OPCODE_LOGIC, OPTYPE_OR, rd, ra, rb)]
def XOR (rd, ra, rb): return [A_FORMAT(OPCODE_LOGIC, OPTYPE_XOR, rd, ra, rb)]

def XCHG(rx, ry): return [*XOR(rx, rx, ry),
*XOR(ry, ry, rx),
*XOR(rx, rx, ry)]

def ADD (rd, ra, rb): return [A_FORMAT(OPCODE_ARITH, OPTYPE_ADD, rd, ra, rb)]
def SUB (rd, ra, rb): return [A_FORMAT(OPCODE_ARITH, OPTYPE_SUB, rd, ra, rb)]
def CMP ( ra, rb): return [A_FORMAT(OPCODE_ARITH, OPTYPE_CMP, 0, ra, rb)]