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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 1c7c75a254c3
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  • 1 commit
  • 3 files changed
  • 1 contributor

Commits on Dec 24, 2018

  1. Copy the full SHA
    1c7c75a View commit details
Showing with 45 additions and 3 deletions.
  1. +2 −1 nmigen/back/rtlil.py
  2. +16 −2 nmigen/hdl/xfrm.py
  3. +27 −0 nmigen/test/test_hdl_xfrm.py
3 changes: 2 additions & 1 deletion nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -620,6 +620,7 @@ def convert_fragment(builder, fragment, name, top):
rhs_compiler = _RHSValueCompiler(compiler_state)
lhs_compiler = _LHSValueCompiler(compiler_state)
stmt_compiler = _StatementCompiler(compiler_state, rhs_compiler, lhs_compiler)
switch_cleaner = xfrm.SwitchCleaner()

verilog_trigger = None
verilog_trigger_sync_emitted = False
@@ -720,7 +721,7 @@ def convert_fragment(builder, fragment, name, top):
stmt_compiler._group = group_signals
stmt_compiler._case = case
stmt_compiler._has_rhs = False
stmt_compiler(fragment.statements)
stmt_compiler(switch_cleaner(fragment.statements))

# Verilog `always @*` blocks will not run if `*` does not match anythng, i.e.
# if the implicit sensitivity list is empty. We check this while translating,
18 changes: 16 additions & 2 deletions nmigen/hdl/xfrm.py
Original file line number Diff line number Diff line change
@@ -13,7 +13,7 @@
"StatementVisitor", "StatementTransformer",
"FragmentTransformer",
"DomainRenamer", "DomainLowerer",
"LHSGroupAnalyzer",
"SwitchCleaner", "LHSGroupAnalyzer",
"ResetInserter", "CEInserter"]


@@ -165,7 +165,7 @@ def on_Assign(self, stmt):
return Assign(self.on_value(stmt.lhs), self.on_value(stmt.rhs))

def on_Switch(self, stmt):
cases = OrderedDict((k, self.on_statement(v)) for k, v in stmt.cases.items())
cases = OrderedDict((k, self.on_statement(s)) for k, s in stmt.cases.items())
return Switch(self.on_value(stmt.test), cases)

def on_statements(self, stmts):
@@ -280,6 +280,20 @@ def on_ResetSignal(self, value):
return cd.rst


class SwitchCleaner(StatementVisitor):
def on_Assign(self, stmt):
return stmt

def on_Switch(self, stmt):
cases = OrderedDict((k, self.on_statement(s)) for k, s in stmt.cases.items())
if any(len(s) for s in stmt.cases.values()):
return Switch(stmt.test, cases)

def on_statements(self, stmts):
stmts = flatten(self.on_statement(stmt) for stmt in stmts)
return _StatementList(stmt for stmt in stmts if stmt is not None)


class LHSGroupAnalyzer(StatementVisitor):
def __init__(self):
self.signals = SignalDict()
27 changes: 27 additions & 0 deletions nmigen/test/test_hdl_xfrm.py
Original file line number Diff line number Diff line change
@@ -158,6 +158,33 @@ def test_lower_wrong_reset_less_domain(self):
DomainLowerer({"sync": sync})(f)


class SwitchCleanerTestCase(FHDLTestCase):
def test_clean(self):
a = Signal()
b = Signal()
c = Signal()
stmts = [
Switch(a, {
1: a.eq(0),
0: [
b.eq(1),
Switch(b, {1: []})
]
})
]

self.assertRepr(SwitchCleaner()(stmts), """
(
(switch (sig a)
(case 1
(eq (sig a) (const 1'd0)))
(case 0
(eq (sig b) (const 1'd1)))
)
)
""")


class LHSGroupAnalyzerTestCase(FHDLTestCase):
def test_no_group_unrelated(self):
a = Signal()