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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: fc0fb9d89fa4
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Dec 24, 2018

  1. back.rtlil: always output negative values as two's complement.

    - is valid in RTLIL but means something entirely different.
    whitequark committed Dec 24, 2018
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    fc0fb9d View commit details
Showing with 2 additions and 1 deletion.
  1. +2 −1 nmigen/back/rtlil.py
3 changes: 2 additions & 1 deletion nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -361,7 +361,8 @@ def on_Const(self, value):
if isinstance(value.value, str):
return "{}'{}".format(value.nbits, value.value)
else:
return "{}'{:0{}b}".format(value.nbits, value.value, value.nbits)
value_twos_compl = value.value & ((1 << value.nbits) - 1)
return "{}'{:0{}b}".format(value.nbits, value_twos_compl, value.nbits)

def on_Signal(self, value):
wire_curr, wire_next = self.s.resolve(value)