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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: fe8cb552041c
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  • 1 commit
  • 2 files changed
  • 1 contributor

Commits on Dec 26, 2018

  1. lib.cdc: add tests for MultiReg.

    whitequark committed Dec 26, 2018
    Copy the full SHA
    fe8cb55 View commit details
Showing with 44 additions and 0 deletions.
  1. +4 −0 nmigen/back/pysim.py
  2. +40 −0 nmigen/test/test_lib_cdc.py
4 changes: 4 additions & 0 deletions nmigen/back/pysim.py
Original file line number Diff line number Diff line change
@@ -7,6 +7,7 @@

from ..tools import flatten
from ..hdl.ast import *
from ..hdl.ir import *
from ..hdl.xfrm import ValueVisitor, StatementVisitor


@@ -359,6 +360,9 @@ def __init__(self, fragment, vcd_file=None, gtkw_file=None, traces=()):
self._gtkw_file = gtkw_file
self._traces = traces

while not isinstance(self._fragment, Fragment):
self._fragment = self._fragment.get_fragment(platform=None)

@staticmethod
def _check_process(process):
if inspect.isgeneratorfunction(process):
40 changes: 40 additions & 0 deletions nmigen/test/test_lib_cdc.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,40 @@
from .tools import *
from ..hdl.ast import *
from ..back.pysim import *
from ..lib.cdc import *


class MultiRegTestCase(FHDLTestCase):
def test_basic(self):
i = Signal()
o = Signal()
frag = MultiReg(i, o)
with Simulator(frag) as sim:
sim.add_clock(1e-6)
def process():
self.assertEqual((yield o), 0)
yield i.eq(1)
yield Tick()
self.assertEqual((yield o), 0)
yield Tick()
self.assertEqual((yield o), 0)
yield Tick()
self.assertEqual((yield o), 1)
sim.add_process(process)

def test_basic(self):
i = Signal(reset=1)
o = Signal()
frag = MultiReg(i, o, reset=1)
with Simulator(frag) as sim:
sim.add_clock(1e-6)
def process():
self.assertEqual((yield o), 1)
yield i.eq(0)
yield Tick()
self.assertEqual((yield o), 1)
yield Tick()
self.assertEqual((yield o), 1)
yield Tick()
self.assertEqual((yield o), 0)
sim.add_process(process)