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When nMigen elaborates an asynchronous read port, it does not wire the latter to a clock signal.
nmigen/nmigen/hdl/mem.py
Line 102 in 43e4833
The following nMigen code instantiates an asynchronous and transparent read port:
from nmigen import * from nmigen.back import verilog class Foo: def __init__(self): mem = Memory(4, 4) self.rp = mem.read_port(synchronous=False, transparent=True) def elaborate(self, platform): m = Module() m.submodules += self.rp return m foo = Foo() frag = foo.elaborate(platform=None) print(verilog.convert(frag))
which produces the following (broken?) output:
/* Generated by Yosys 0.8+147 (git sha1 266511b2, gcc 8.2.1 -fPIC -Os) */ (* top = 1 *) (* generator = "nMigen" *) module top(mem_r_addr); (* src = "/home/jf/src/nmigen/nmigen/hdl/mem.py:86" *) input [1:0] mem_r_addr; (* src = "/home/jf/src/nmigen/nmigen/hdl/mem.py:88" *) wire [3:0] mem_r_data; reg [3:0] mem [3:0]; initial begin mem[0] = 4'h0; mem[1] = 4'h0; mem[2] = 4'h0; mem[3] = 4'h0; end reg [1:0] _0_; always @(posedge 1'h0) begin _0_ <= mem_r_addr; end assign mem_r_data = mem[_0_]; endmodule
The Yosys Verilog backend seems to make transparent read ports rely on the presence of a clock input regardless of them being synchronous or not. https://github.com/YosysHQ/yosys/blob/266511b29eb66486bd17210eb28454a2efee218a/backends/verilog/verilog_backend.cc#L1104-L1109
Removing the if self.synchronous else Const(0) in the mem.py snippet above seems to work, but it makes asynchronous read ports rely on a clock signal.
if self.synchronous else Const(0)
This behaviour can currently be encountered when instantiating a SyncFIFO with fwft=True.
fwft=True
The text was updated successfully, but these errors were encountered:
Upstream bug: YosysHQ/yosys#802.
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Fixed upstream.
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When nMigen elaborates an asynchronous read port, it does not wire the latter to a clock signal.
nmigen/nmigen/hdl/mem.py
Line 102 in 43e4833
The following nMigen code instantiates an asynchronous and transparent read port:
which produces the following (broken?) output:
The Yosys Verilog backend seems to make transparent read ports rely on the presence of a clock input regardless of them being synchronous or not.
https://github.com/YosysHQ/yosys/blob/266511b29eb66486bd17210eb28454a2efee218a/backends/verilog/verilog_backend.cc#L1104-L1109
Removing the
if self.synchronous else Const(0)
in the mem.py snippet above seems to work, but it makes asynchronous read ports rely on a clock signal.This behaviour can currently be encountered when instantiating a SyncFIFO with
fwft=True
.The text was updated successfully, but these errors were encountered: