Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: whitequark/glasgow
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 46f6594e1ae8
Choose a base ref
...
head repository: whitequark/glasgow
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 9cc3d9a48161
Choose a head ref
  • 3 commits
  • 2 files changed
  • 1 contributor

Commits on Feb 26, 2019

  1. applet.jtag_mips: reset Rocc before entering probe mode.

    Otherwise all our writes will just get ignored.
    
    This commit also adds detection of unexpected core reset.
    whitequark committed Feb 26, 2019
    Copy the full SHA
    034d01f View commit details

Commits on Feb 27, 2019

  1. applet.jtag: reset TAP chain before selecting a TAP.

    Selecting a TAP requires reading IDCODE/BYPASS from DR, which means
    that a TAP chain reset was a precondition for select_tap(), but this
    wasn't intended or documented. The current design requires a reset,
    so just add that.
    
    Since all derived applets want to select a TAP, remove the TAP reset
    via TMS from run(); however, keep TAP reset via TRST#, because that
    enables the TRST# driver.
    whitequark committed Feb 27, 2019
    Copy the full SHA
    fef9fff View commit details
  2. Copy the full SHA
    9cc3d9a View commit details
Showing with 16 additions and 5 deletions.
  1. +8 −1 software/glasgow/applet/jtag/__init__.py
  2. +8 −4 software/glasgow/applet/jtag_mips/__init__.py
9 changes: 8 additions & 1 deletion software/glasgow/applet/jtag/__init__.py
Original file line number Diff line number Diff line change
@@ -547,6 +547,8 @@ def segment_irs(self, ir_value, count=None):
return irs

async def select_tap(self, tap, max_ir_length=128, max_dr_length=1024):
await self.test_reset()

dr_value = await self.scan_dr(max_dr_length)
if dr_value is None:
return
@@ -666,8 +668,8 @@ async def run(self, device, args, reset=True):
iface = await device.demultiplexer.claim_interface(self, self.mux_interface, args)
jtag_iface = JTAGInterface(iface, self.logger)
if reset:
# If we have a defined TRST#, enable the driver and reset the TAPs to a good state.
await jtag_iface.pulse_trst()
await jtag_iface.test_reset()
return jtag_iface

@classmethod
@@ -724,6 +726,8 @@ def add_interact_arguments(cls, parser):

async def interact(self, device, args, jtag_iface):
if args.operation in ("scan", "enumerate-ir"):
await jtag_iface.test_reset()

dr_value = await jtag_iface.scan_dr(max_length=args.max_dr_length)
if dr_value is None:
self.logger.warning("DR length scan did not terminate")
@@ -774,6 +778,9 @@ async def interact(self, device, args, jtag_iface):

tap_iface = await jtag_iface.select_tap(tap_index,
args.max_ir_length, args.max_dr_length)
if not tap_iface:
raise GlasgowAppletError("cannot select TAP #%d" % tap_index)

for ir_value in range(0, (1 << ir_length)):
ir_value = bitarray([ir_value & (1 << bit) for bit in range(ir_length)],
endian="little")
12 changes: 8 additions & 4 deletions software/glasgow/applet/jtag_mips/__init__.py
Original file line number Diff line number Diff line change
@@ -66,10 +66,13 @@ async def _exchange_control(self, **fields):
await self.lower.write_ir(IR_CONTROL)

control_bits = await self.lower.exchange_dr(control_bits)
control = DR_CONTROL.from_bitarray(control_bits)
self._log("read CONTROL %s", control.bits_repr(omit_zero=True))
new_control = DR_CONTROL.from_bitarray(control_bits)
self._log("read CONTROL %s", new_control.bits_repr(omit_zero=True))

return control
if new_control.Rocc and control.Rocc:
raise GlasgowAppletError("target has been unexpectedly reset")

return new_control

async def _enable_probe(self):
self._control.ProbEn = 1
@@ -197,7 +200,8 @@ async def _probe(self):
self._DRSEG_DBMn_addr = DRSEG_DBMn_addr
self._DRSEG_DBVn_addr = DRSEG_DBVn_addr

control = await self._exchange_control()
# Start by acknowledging any reset.
control = await self._exchange_control(Rocc=0)
if control.DM:
raise GlasgowAppletError("target already in debug mode")