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The following MWE generates invalid RTLIL and as such fails Verilog generation.
from nmigen import * from nmigen.cli import main class Test: def __init__(self): self.out = Signal(8) def get_fragment(self, platform): data = [0b100, 0b1000, 0b10000] arr = Array(data) idx = Signal(max=len(data)) m = Module() m.d.comb += self.out.eq(arr[idx]) m.d.sync += idx.eq(idx + 1) return m.lower(platform) test = Test() main(test, ports=[test.out])
The following error is produced:
D:\test> python test.py generate -t v test.v Traceback (most recent call last): File "test.py", line 19, in <module> main(test, ports=[test.out]) File "D:\Program Files\Python36\lib\site-packages\nmigen-0.1-py3.6.egg\nmigen\cli.py", line 74, in main main_runner(parser, parser.parse_args(), *args, **kwargs) File "D:\Program Files\Python36\lib\site-packages\nmigen-0.1-py3.6.egg\nmigen\cli.py", line 56, in main_runner output = verilog.convert(fragment, name=name, ports=ports) File "D:\Program Files\Python36\lib\site-packages\nmigen-0.1-py3.6.egg\nmigen\back\verilog.py", line 37, in convert raise YosysError(error.strip()) nmigen.back.verilog.YosysError: ERROR: Found error in internal cell \top.$5 ($pos) at kernel/rtlil.cc:704: attribute \src "test.py:14" cell $pos $5 parameter \Y_WIDTH 8 parameter \A_WIDTH 5 parameter \A_SIGNED 0 connect \Y $4 connect \A 4'1000 end
This error does not occur when the elements of the Array all have the same shape (i.e. [0b100, 0b101, 0b111, 0b110]).
Array
[0b100, 0b101, 0b111, 0b110]
The text was updated successfully, but these errors were encountered:
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The following MWE generates invalid RTLIL and as such fails Verilog generation.
The following error is produced:
This error does not occur when the elements of the
Array
all have the same shape (i.e.[0b100, 0b101, 0b111, 0b110]
).The text was updated successfully, but these errors were encountered: