Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/nmigen
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 39eb2e8fa7ad
Choose a base ref
...
head repository: m-labs/nmigen
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: ae3c5834ed84
Choose a head ref
  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Dec 31, 2018

  1. back.rtlil: fix typo.

    whitequark committed Dec 31, 2018
    Copy the full SHA
    cdc40ea View commit details
  2. back.rtlil: match shape of Array elements to ArrayProxy shape.

    Fixes #15.
    whitequark committed Dec 31, 2018
    Copy the full SHA
    ae3c583 View commit details
Showing with 8 additions and 3 deletions.
  1. +8 −3 nmigen/back/rtlil.py
11 changes: 8 additions & 3 deletions nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -328,9 +328,10 @@ def on_ArrayProxy(self, value):
index = self.s.expand(value.index)
if isinstance(index, ast.Const):
if index.value < len(value.elems):
return self(value.elems[index.value])
elem = value.elems[index.value]
else:
return self(value.elems[-1])
elem = value.elems[-1]
return self.match_shape(elem, *value.shape())
else:
raise LegalizeValue(value.index, range(len(value.elems)))

@@ -503,6 +504,10 @@ def on_Const(self, value):
def on_Operator(self, value):
raise TypeError # :nocov:

def match_shape(self, value, new_bits, new_sign):
assert value.shape() == (new_bits, new_sign)
return self(value)

def on_Signal(self, value):
wire_curr, wire_next = self.s.resolve(value)
if wire_next is None:
@@ -557,7 +562,7 @@ def on_Assign(self, stmt):
else:
# In RTLIL, LHS and RHS of assignment must have exactly same width.
rhs_sigspec = self.rhs_compiler.match_shape(
stmt.rhs, lhs_bits, rhs_sign)
stmt.rhs, lhs_bits, lhs_sign)
self._case.assign(self.lhs_compiler(stmt.lhs), rhs_sigspec)

def on_Switch(self, stmt):