whitequark · Dec 31, 2018
diff --git a/doc/design.ods b/doc/design.ods
diff --git a/doc/manual/insns/LD.tex b/doc/manual/insns/LD.tex
@@ -1,4 +1,4 @@
-\begin{instruction}{LD}{Load with Address in Register}
+\begin{instruction}{LD}{Load}
   \begin{encoding*}{short}
     \mnemonic & \op{3}{010} & \op{2}{00} & \reg{d} & \reg{a} & \off{5} \\
   \end{encoding*}
@@ -7,8 +7,8 @@
     \mnemonic & \op{3}{010} & \op{2}{00} & \reg{d} & \reg{a} & \off{5} \\
   \end{encoding*}
   \assembly{\mnemonic{} Rd, Ra, off}
-  \purpose{To load a word from memory at an absolute address contained in a register, with a constant offset.}
-  \input{mem-restrictions.tex}
+  \purpose{To load a word from memory at a variable address, with a constant offset.}
+  \input{mem5-restrictions.tex}
 \begin{operation}\off{5}
 addr ← mem[W|Ra] + off
 temp ← mem[addr]

diff --git a/doc/manual/insns/LDI.tex b/doc/manual/insns/LDI.tex
@@ -1,16 +1,16 @@
-\begin{instruction}{LDI}{Load PC-relative with Immediate Offset}
+\begin{instruction}{LDI}{Load Indexed}
   \begin{encoding*}{short}
-    \mnemonic & \op{3}{011} & \op{2}{00} & \reg{d} & \off{8} \\
+    \mnemonic & \op{3}{011} & \op{2}{00} & \reg{d} & \reg{a} & \off{5} \\
   \end{encoding*}
   \begin{encoding*}{long}
     \exti
-    \mnemonic & \op{3}{011} & \op{2}{00} & \reg{d} & \off{8} \\
+    \mnemonic & \op{3}{011} & \op{2}{00} & \reg{d} & \reg{a} & \off{5} \\
   \end{encoding*}
-  \assembly{\mnemonic{} Rd, off}
-  \purpose{To load a word from memory at an address relative to PC with a constant offset.}
-  \input{memi-restrictions.tex}
+  \assembly{\mnemonic{} Rd, Ra, off}
+  \purpose{To load a word from memory at a constant PC-relative address, with a variable offset.}
+  \input{mem5-restrictions.tex}
 \begin{operation}\off{8}
-addr ← PC + off
+addr ← PC + mem[W|Ra] + off
 temp ← mem[addr]
 mem[W|Rd] ← temp
 \end{operation}

diff --git a/doc/manual/insns/LDX.tex b/doc/manual/insns/LDX.tex
@@ -1,4 +1,4 @@
-\begin{instruction}{LDX}{Load External with Address in Register}
+\begin{instruction}{LDX}{Load External}
   \begin{encoding*}{short}
     \mnemonic & \op{3}{010} & \op{2}{10} & \reg{d} & \reg{a} & \off{5} \\
   \end{encoding*}
@@ -7,8 +7,8 @@
     \mnemonic & \op{3}{010} & \op{2}{10} & \reg{d} & \reg{a} & \off{5} \\
   \end{encoding*}
   \assembly{\mnemonic{} Rd, Ra, off}
-  \purpose{To complete a load cycle on external bus at an absolute address contained in a register, with a constant offset.}
-  \input{mem-restrictions.tex}
+  \purpose{To complete a load cycle on external bus at a variable address, with a constant offset.}
+  \input{mem5-restrictions.tex}
 \begin{operation}\off{5}
 addr ← mem[W|Ra] + off
 temp ← ext[addr]

diff --git a/doc/manual/insns/LDXI.tex → doc/manual/insns/LDXZ.tex b/doc/manual/insns/LDXI.tex → doc/manual/insns/LDXZ.tex
@@ -1,4 +1,4 @@
-\begin{instruction}{LDXI}{Load External with Immediate Address}
+\begin{instruction}{LDXZ}{Load External Absolute}
   \begin{encoding*}{short}
     \mnemonic & \op{3}{011} & \op{2}{10} & \reg{d} & \off{8} \\
   \end{encoding*}
@@ -8,7 +8,7 @@
   \end{encoding*}
   \assembly{\mnemonic{} Rd, off}
   \purpose{To complete a load cycle on external bus at a constant absolute address.}
-  \input{memi-restrictions.tex}
+  \input{mem8-restrictions.tex}
 \begin{operation}\off{8}
 temp ← ext[off]
 mem[W|Rd] ← temp

diff --git a/doc/manual/insns/ST.tex b/doc/manual/insns/ST.tex
@@ -1,4 +1,4 @@
-\begin{instruction}{ST}{Store with Address in Register}
+\begin{instruction}{ST}{Store}
   \begin{encoding*}{short}
     \mnemonic & \op{3}{010} & \op{2}{01} & \reg{s} & \reg{a} & \off{5} \\
   \end{encoding*}
@@ -7,8 +7,8 @@
     \mnemonic & \op{3}{010} & \op{2}{01} & \reg{s} & \reg{a} & \off{5} \\
   \end{encoding*}
   \assembly{\mnemonic{} Rs, Ra, off}
-  \purpose{To store a word to memory at an absolute address contained in a register, with a constant offset.}
-  \input{mem-restrictions.tex}
+  \purpose{To store a word to memory at a variable address, with a constant offset.}
+  \input{mem5-restrictions.tex}
 \begin{operation}\off{5}
 addr ← mem[W|Ra] + off
 temp ← mem[W|Rs]

diff --git a/doc/manual/insns/STI.tex b/doc/manual/insns/STI.tex
@@ -1,16 +1,16 @@
-\begin{instruction}{STI}{Store PC-relative with Immediate Offset}
+\begin{instruction}{STI}{Store Indexed}
   \begin{encoding*}{short}
-    \mnemonic & \op{3}{011} & \op{2}{01} & \reg{s} & \off{8} \\
+    \mnemonic & \op{3}{010} & \op{2}{01} & \reg{s} & \reg{a} & \off{5} \\
   \end{encoding*}
   \begin{encoding*}{long}
     \exti
-    \mnemonic & \op{3}{011} & \op{2}{01} & \reg{s} & \off{8} \\
+    \mnemonic & \op{3}{010} & \op{2}{01} & \reg{s} & \reg{a} & \off{5} \\
   \end{encoding*}
-  \assembly{\mnemonic{} Rs, off}
-  \purpose{To store a word to memory at an address relative to PC with a constant offset.}
-  \input{memi-restrictions.tex}
+  \assembly{\mnemonic{} Rs, Ra, off}
+  \purpose{To store a word to memory at a constant PC-relative address, with a variable offset.}
+  \input{mem5-restrictions.tex}
 \begin{operation}\off{8}
-addr ← PC + off
+addr ← PC + mem[W|Ra] + off
 temp ← mem[W|Rs]
 mem[addr] ← temp
 \end{operation}

diff --git a/doc/manual/insns/STX.tex b/doc/manual/insns/STX.tex
@@ -7,8 +7,8 @@
     \mnemonic & \op{3}{010} & \op{2}{11} & \reg{s} & \reg{a} & \off{5} \\
   \end{encoding*}
   \assembly{\mnemonic{} Rs, Ra, off}
-  \purpose{To complete a store cycle on external bus at an absolute address contained in a register, with a constant offset.}
-  \input{mem-restrictions.tex}
+  \purpose{To complete a store cycle on external bus at a variable address, with a constant offset.}
+  \input{mem5-restrictions.tex}
 \begin{operation}\off{5}
 addr ← mem[W|Ra] + off
 temp ← mem[W|Rs]

diff --git a/doc/manual/insns/STXI.tex → doc/manual/insns/STXZ.tex b/doc/manual/insns/STXI.tex → doc/manual/insns/STXZ.tex
@@ -1,4 +1,4 @@
-\begin{instruction}{STXI}{Store External with Immediate Address}
+\begin{instruction}{STXZ}{Store External Absolute}
   \begin{encoding*}{short}
     \mnemonic & \op{3}{011} & \op{2}{11} & \reg{s} & \off{8} \\
   \end{encoding*}
@@ -8,7 +8,7 @@
   \end{encoding*}
   \assembly{\mnemonic{} Rs, off}
   \purpose{To complete a store cycle on external bus at a constant absolute address.}
-  \input{mem-restrictions.tex}
+  \input{mem8-restrictions.tex}
 \begin{operation}\off{8}
 temp ← mem[W|Rs]
 ext[off] ← temp

diff --git a/doc/manual/insns/index.tex b/doc/manual/insns/index.tex
@@ -117,13 +117,6 @@
   }{
     \end{adjustwidth}
   }
-
-  \newenvironment{notice}{
-    \cbcolor{red}
-    \par\textbf{Notice:}\cbstart\par
-  }{
-    \cbend
-  }
 }{
   \pagebreak
 }
@@ -165,7 +158,7 @@
 \input{LD.tex}
 \input{LDI.tex}
 \input{LDX.tex}
-\input{LDXI.tex}
+\input{LDXZ.tex}
 \input{LEAV.tex} % pseudo
 \input{MOV.tex} % pseudo
 \input{MOVA.tex}
@@ -187,7 +180,7 @@
 \input{ST.tex}
 \input{STI.tex}
 \input{STX.tex}
-\input{STXI.tex}
+\input{STXZ.tex}
 \input{SUB.tex}
 \input{SUBI.tex}
 % \input{SWPW.tex}

diff --git a/doc/manual/insns/mem-restrictions.tex → doc/manual/insns/mem5-restrictions.tex b/doc/manual/insns/mem-restrictions.tex → doc/manual/insns/mem5-restrictions.tex
diff --git a/doc/manual/insns/memi-restrictions.tex → doc/manual/insns/mem8-restrictions.tex b/doc/manual/insns/memi-restrictions.tex → doc/manual/insns/mem8-restrictions.tex
diff --git a/doc/manual/manual.pdf b/doc/manual/manual.pdf
diff --git a/doc/manual/manual.tex b/doc/manual/manual.tex
@@ -25,6 +25,13 @@
 \newcommand{\unpredictable}{\textbf{UNPREDICTABLE}}
 \uchyph=0
 
+\newenvironment{notice}{
+  \cbcolor{red}
+  \par\textbf{Notice:}\cbstart\par
+}{
+  \cbend
+}
+
 \begin{document}
 
 \begin{titlepage}
@@ -35,6 +42,12 @@
   \par{\Huge Architecture Reference Manual}
 \end{titlepage}
 
+\begin{notice}
+This document is a work in progress and subject to change without warning. However, the parts that are \textit{especially} subject to change carry a notice similar to this one.
+\end{notice}
+
+\pagebreak
+
 \tableofcontents
 \addcontentsline{toc}{section}{Table of Contents}
 \pagebreak