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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 7acea8f3ce84
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  • 2 commits
  • 6 files changed
  • 1 contributor

Commits on Jan 26, 2019

  1. Copy the full SHA
    b133eb7 View commit details
  2. examples: update for newer API.

    whitequark committed Jan 26, 2019
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    7acea8f View commit details
Showing with 11 additions and 13 deletions.
  1. +4 −4 examples/arst.py
  2. +1 −1 examples/cdc.py
  3. +3 −5 examples/ctr_ce.py
  4. +1 −1 examples/por.py
  5. +1 −1 examples/tbuf.py
  6. +1 −1 nmigen/back/rtlil.py
8 changes: 4 additions & 4 deletions examples/arst.py
Original file line number Diff line number Diff line change
@@ -15,7 +15,7 @@ def elaborate(self, platform):


if __name__ == "__main__":
ctr = ClockDivisor(factor=16)
frag = ctr.elaborate(platform=None)
frag.add_domains(ClockDomain("sync", async_reset=True))
main(frag, ports=[ctr.o])
ctr = ClockDivisor(factor=16)
m = ctr.elaborate(platform=None)
m.domains += ClockDomain("sync", async_reset=True)
main(m, ports=[ctr.o])
2 changes: 1 addition & 1 deletion examples/cdc.py
Original file line number Diff line number Diff line change
@@ -7,4 +7,4 @@
m.submodules += MultiReg(i, o)

if __name__ == "__main__":
main(m.lower(platform=None), ports=[i, o])
main(m, ports=[i, o])
8 changes: 3 additions & 5 deletions examples/ctr_ce.py
Original file line number Diff line number Diff line change
@@ -15,13 +15,11 @@ def elaborate(self, platform):
return CEInserter(self.ce)(m.lower(platform))


ctr = Counter(width=16)
frag = ctr.elaborate(platform=None)
ctr = Counter(width=16)

# print(rtlil.convert(frag, ports=[ctr.o, ctr.ce]))
print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))
print(verilog.convert(ctr, ports=[ctr.o, ctr.ce]))

with pysim.Simulator(frag,
with pysim.Simulator(ctr,
vcd_file=open("ctrl.vcd", "w"),
gtkw_file=open("ctrl.gtkw", "w"),
traces=[ctr.ce, ctr.v, ctr.o]) as sim:
2 changes: 1 addition & 1 deletion examples/por.py
Original file line number Diff line number Diff line change
@@ -16,4 +16,4 @@
]

if __name__ == "__main__":
main(m.lower(platform=None), ports=[cd_por.clk])
main(m, ports=[cd_por.clk])
2 changes: 1 addition & 1 deletion examples/tbuf.py
Original file line number Diff line number Diff line change
@@ -9,4 +9,4 @@
m.submodules += pin_t.get_tristate(pin)

if __name__ == "__main__":
main(m.lower(platform=None), ports=[pin, pin_t.oe, pin_t.i, pin_t.o])
main(m, ports=[pin, pin_t.oe, pin_t.i, pin_t.o])
2 changes: 1 addition & 1 deletion nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -844,7 +844,7 @@ def convert_fragment(builder, fragment, name, top):


def convert(fragment, name="top", **kwargs):
fragment = fragment.prepare(**kwargs)
fragment = ir.Fragment.get(fragment, platform=None).prepare(**kwargs)
builder = _Builder()
convert_fragment(builder, fragment, name=name, top=True)
return str(builder)