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base repository: m-labs/nmigen
base: ae0cb48fbb4f
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head repository: m-labs/nmigen
compare: 59c7540aeb08
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Dec 22, 2018

  1. back.rtlil: remove useless condition. NFC.

    whitequark committed Dec 22, 2018
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  2. back.rtlil: split processes as finely as possible. 

    This makes simulation work correctly (by introducing delta cycles,
and therefore, making the overall Verilog simulation deterministic)
at the price of pessimizing mux trees generated by Yosys and Synplify
frontends, sometimes severely.
    whitequark committed Dec 22, 2018
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    59c7540 View commit details
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