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base repository: m-labs/nmigen
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base: 6ee80408bbb5
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head repository: m-labs/nmigen
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compare: 99b778158d80
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Dec 22, 2018

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    8730895 View commit details
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    99b7781 View commit details
Showing with 22 additions and 7 deletions.
  1. +3 −2 nmigen/compat/genlib/fsm.py
  2. +19 −5 nmigen/hdl/mem.py
5 changes: 3 additions & 2 deletions nmigen/compat/genlib/fsm.py
Original file line number Diff line number Diff line change
@@ -77,8 +77,9 @@ def on_unknown_statement(self, node):
next_value_ce, next_value = self._get_register_control(node.target)
except KeyError:
related = node.target if isinstance(node.target, Signal) else None
next_value = Signal(node.target.shape())
next_value_ce = Signal()
next_value = Signal(node.target.shape(),
name="{}_fsm_next".format(node.target.name))
next_value_ce = Signal(name="{}_fsm_next_ce".format(node.target.name))
self.registers.append((node.target, next_value_ce, next_value))
return next_value.eq(node.value), next_value_ce.eq(1)
else:
24 changes: 19 additions & 5 deletions nmigen/hdl/mem.py
Original file line number Diff line number Diff line change
@@ -27,15 +27,29 @@ def __init__(self, width, depth, init=None, name=None):
self.width = width
self.depth = depth

self.init = [] if init is None else list(init)
# Array of signals for simulation.
self._array = Array()
for addr in range(self.depth):
self._array.append(Signal(self.width, name="{}({})".format(name, addr)))

self.init = init

@property
def init(self):
return self._init

@init.setter
def init(self, new_init):
self._init = [] if new_init is None else list(new_init)
if len(self.init) > self.depth:
raise ValueError("Memory initialization value count exceed memory depth ({} > {})"
.format(len(self.init), self.depth))

# Array of signals for simulation.
self._array = Array()
for addr, data in enumerate(self.init + [0 for _ in range(self.depth - len(self.init))]):
self._array.append(Signal(self.width, reset=data, name="{}({})".format(name, addr)))
for addr in range(self.depth):
if addr < len(self._init):
self._array[addr].reset = self._init[addr]
else:
self._array[addr].reset = 0

def read_port(self, domain="sync", synchronous=True, transparent=True):
if not synchronous and not transparent: