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base repository: m-labs/nmigen
base: 99b778158d80
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head repository: m-labs/nmigen
compare: 37b81309d3aa
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  • 1 commit
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Commits on Dec 22, 2018

  1. back.rtlil: always initialize the entire memory. 

    This avoids reading 'x from the memory in simulation. In general,
FPGA memories can only be initialized in block granularity, and
zero-initializing is cheap, so this is not a significant issue with
resource consumption.
    whitequark committed Dec 22, 2018
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