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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 37b81309d3aa
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Dec 22, 2018

  1. back.rtlil: always initialize the entire memory.

    This avoids reading 'x from the memory in simulation. In general,
    FPGA memories can only be initialized in block granularity, and
    zero-initializing is cheap, so this is not a significant issue with
    resource consumption.
    whitequark committed Dec 22, 2018
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    37b8130 View commit details
Showing with 5 additions and 1 deletion.
  1. +5 −1 nmigen/back/rtlil.py
6 changes: 5 additions & 1 deletion nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -624,7 +624,11 @@ def convert_fragment(builder, fragment, name, top):
memories[memory] = module.memory(width=memory.width, size=memory.depth,
name=memory.name)
addr_bits = bits_for(memory.depth)
for addr, data in enumerate(memory.init):
for addr in range(memory.depth):
if addr < len(memory.init):
data = memory.init[addr]
else:
data = 0
module.cell("$meminit", ports={
"\\ADDR": rhs_compiler(ast.Const(addr, addr_bits)),
"\\DATA": rhs_compiler(ast.Const(data, memory.width)),