Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/nmigen
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 92a96e164460
Choose a base ref
...
head repository: m-labs/nmigen
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 39eb2e8fa7ad
Choose a head ref
  • 2 commits
  • 4 files changed
  • 1 contributor

Commits on Dec 29, 2018

  1. back.pysim: warn if simulation is not run.

    This would have prevented 3ea35b8.
    whitequark committed Dec 29, 2018
    Copy the full SHA
    849c649 View commit details
  2. lib.cdc: fix tests to actually run.

    whitequark committed Dec 29, 2018
    Copy the full SHA
    39eb2e8 View commit details
Showing with 19 additions and 1 deletion.
  1. +10 −0 nmigen/back/pysim.py
  2. +1 −1 nmigen/hdl/ast.py
  3. +2 −0 nmigen/test/test_lib_cdc.py
  4. +6 −0 nmigen/test/test_sim.py
10 changes: 10 additions & 0 deletions nmigen/back/pysim.py
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
import math
import inspect
import warnings
from contextlib import contextmanager
from bitarray import bitarray
from vcd import VCDWriter
@@ -365,6 +366,8 @@ def __init__(self, fragment, vcd_file=None, gtkw_file=None, traces=()):
self._gtkw_file = gtkw_file
self._traces = traces

self._run_called = False

while not isinstance(self._fragment, Fragment):
self._fragment = self._fragment.get_fragment(platform=None)

@@ -755,17 +758,24 @@ def step(self, run_passive=False):
return False

def run(self):
self._run_called = True

while self.step():
pass

def run_until(self, deadline, run_passive=False):
self._run_called = True

while self._timestamp < deadline:
if not self.step(run_passive):
return False

return True

def __exit__(self, *args):
if not self._run_called:
warnings.warn("Simulation created, but not run", UserWarning)

if self._vcd_writer:
vcd_timestamp = (self._timestamp + self._delta) / self._epsilon
self._vcd_writer.close(vcd_timestamp)
2 changes: 1 addition & 1 deletion nmigen/hdl/ast.py
Original file line number Diff line number Diff line change
@@ -860,7 +860,7 @@ def __repr__(self):


class Tick(Statement):
def __init__(self, domain):
def __init__(self, domain="sync"):
self.domain = str(domain)

def _rhs_signals(self):
2 changes: 2 additions & 0 deletions nmigen/test/test_lib_cdc.py
Original file line number Diff line number Diff line change
@@ -21,6 +21,7 @@ def process():
yield Tick()
self.assertEqual((yield o), 1)
sim.add_process(process)
sim.run()

def test_basic(self):
i = Signal(reset=1)
@@ -38,3 +39,4 @@ def process():
yield Tick()
self.assertEqual((yield o), 0)
sim.add_process(process)
sim.run()
6 changes: 6 additions & 0 deletions nmigen/test/test_sim.py
Original file line number Diff line number Diff line change
@@ -530,3 +530,9 @@ def process():
self.assertEqual((yield self.rdport.data), 0x33)
sim.add_clock(1e-6)
sim.add_process(process)

def test_wrong_not_run(self):
with self.assertWarns(UserWarning,
msg="Simulation created, but not run"):
with Simulator(Fragment()) as sim:
pass