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base repository: whitequark/glasgow
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head repository: whitequark/glasgow
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compare: 730ccd6f5e57
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Feb 27, 2019

  1. applet.jtag_mips: update the lists of tested configurations.

    @whitequark
    whitequark committed Feb 27, 2019
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    5411dec View commit details

  2. applet.jtag: enumerate-ir: make more robust to missing DRs. 

    A missing DR is a DR that leaves TDO unconnected when it is selected.
    @whitequark
    whitequark committed Feb 27, 2019
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    730ccd6 View commit details
Showing with 15 additions and 7 deletions.
  1. +7 −3 software/glasgow/applet/jtag/__init__.py
  2. +8 −4 software/glasgow/applet/jtag_mips/__init__.py
10 changes: 7 additions & 3 deletions software/glasgow/applet/jtag/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -628,9 +628,10 @@ async def write_dr(self, data):
async def scan_dr_length(self, max_length, zero_ok=False):
length = await self.lower.scan_dr_length(max_length=self._dr_overhead + max_length,
zero_ok=zero_ok)
if length is None:
if length is None or length == 0:
return
assert length >= self._dr_overhead
assert zero_ok or length - self._dr_overhead > 0
return length - self._dr_overhead


@@ -788,13 +789,16 @@ async def interact(self, device, args, jtag_iface):
await tap_iface.write_ir(ir_value)
dr_length = await tap_iface.scan_dr_length(max_length=args.max_dr_length,
zero_ok=True)
if dr_length == 0:
if dr_length is None:
level = logging.ERROR
dr_length = "?"
elif dr_length == 0:
level = logging.WARN
elif dr_length == 1:
level = logging.DEBUG
else:
level = logging.INFO
self.logger.log(level, " IR=%s DR[%d]", ir_value.to01(), dr_length)
self.logger.log(level, " IR=%s DR[%s]", ir_value.to01(), dr_length)

if args.operation == "jtag-repl":
await AsyncInteractiveConsole(locals={"jtag_iface":jtag_iface}).interact()
12 changes: 8 additions & 4 deletions software/glasgow/applet/jtag_mips/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -166,7 +166,7 @@ async def _probe(self):
self._check_state("probe", "Probe")

await self._read_impcode()
self._logger.info("found CPU with IMPCODE=%#10x", self._impcode.to_int())
self._logger.info("found CPU with IMPCODE=%#010x", self._impcode.to_int())

await self._scan_address_length()

@@ -814,9 +814,13 @@ class JTAGMIPSApplet(JTAGApplet, name="jtag-mips"):
* Tracepoints and watchpoints.
The applet has been written with 32- and 64-bit CPUs with EJTAG 1.x-5.x in mind, but has only
been tested on a big endian MIPS32 R1 EJTAG 1.x/2.0 CPU. As such, use with any other CPUs
might or might not be possible. In particular, it certainly does not currently work on
little-endian CPUs. Sorry about that.
been tested with the following configurations:
* MIPS32 R1 big endian with EJTAG 1.x/2.0 (BCM6358);
* MIPS32 R1 big endian with EJTAG 2.6 (Infineon ADM5120).
Other configurations might or might not work. In particular, it certainly does not currently
work on little-endian CPUs. Sorry about that.
"""

@classmethod