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Unassigned signals do not assume their reset values #35

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jfng opened this issue Feb 5, 2019 · 1 comment
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Unassigned signals do not assume their reset values #35

jfng opened this issue Feb 5, 2019 · 1 comment
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backend:RTLIL bug
Milestone
0.1

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@jfng
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jfng commented Feb 5, 2019

Leaving a Signal unassigned does not make it assume its reset value when used as the RHS of an assignment.

Consider the following snippet:

from nmigen import *
from nmigen.back import rtlil


class Foo:
    def elaborate(self, platform):
        m = Module()

        foo = Signal(reset=1)
        bar = Signal()
        m.d.comb += bar.eq(foo)

        return m


foo = Foo()
frag = foo.elaborate(platform=None)
print(rtlil.convert(frag))

which produces the following IR:

attribute \generator "nMigen"
attribute \top 1
module \top
  attribute \src "foo.py:9"
  wire width 1 input 0 \foo
  attribute \src "foo.py:10"
  wire width 1 \bar
  attribute \src "foo.py:10"
  wire width 1 $next\bar
  process $group_0
    assign $next\bar 1'0
    assign $next\bar \foo
    sync init
    sync always
      update \bar $next\bar
  end
end

Should \foo be set to its reset value instead of being propagated as an input ?
@whitequark
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Duplicate of #30.

@sbourdeauducq sbourdeauducq mentioned this issue Feb 14, 2019
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@whitequark whitequark reopened this May 12, 2019
whitequark added a commit that referenced this issue May 13, 2019
back.rtlil: assign undriven signals to their reset value.
921f506 
Fixes #35.
@whitequark whitequark added this to the 0.1 milestone Jun 28, 2019
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backend:RTLIL bug
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@whitequark @jfng