whitequark · Feb 6, 2019 · Feb 6, 2019 · Feb 6, 2019
Showing with 34 additions and 38 deletions.

+2 −2 firmware/fpga.c

+10 −26 software/glasgow/access/direct/multiplexer.py

+20 −7 software/glasgow/platform/__init__.py

+2 −3 software/glasgow/target/hardware.py
diff --git a/firmware/fpga.c b/firmware/fpga.c
@@ -14,10 +14,10 @@ void fpga_reset() {
   delay_us(1);
 
   // Configure config pins while FPGA is in reset.
-  IOB |=  (1<<PINB_SCK);
-  IOB &= ~(1<<PINB_SS_N);
   OEA &= ~(1<<PINA_CDONE);
   OEB |=  (1<<PINB_SCK)|(1<<PINB_SS_N)|(1<<PINB_SI);
+  IOB |=  (1<<PINB_SCK);
+  IOB &= ~(1<<PINB_SS_N);
 
   // Release FPGA reset.
   IOD |=  (1<<PIND_CRESET_N);

diff --git a/software/glasgow/access/direct/multiplexer.py b/software/glasgow/access/direct/multiplexer.py
@@ -89,7 +89,6 @@ def claim_interface(self, applet, args, with_analyzer=True, throttle="fifo"):
         self._claimed_pipes += 1
 
         pins = []
-        pin_names = []
         if hasattr(args, "port_spec"):
             iface_spec = list(args.port_spec)
 
@@ -105,9 +104,8 @@ def claim_interface(self, applet, args, with_analyzer=True, throttle="fifo"):
                     applet.logger.error("port %s does not exist", port)
                     return None
                 else:
-                    port_signal = self._ports[port]()
-                    pins += [port_signal[bit] for bit in range(port_signal.nbits)]
-                    pin_names += ["{}{}".format(port, bit) for bit in range(port_signal.nbits)]
+                    port_width, port_req = self._ports[port]
+                    pins += [(port, bit, port_req) for bit in range(port_width)]
         else:
             iface_spec = []
 
@@ -125,13 +123,13 @@ def claim_interface(self, applet, args, with_analyzer=True, throttle="fifo"):
                                 self._pipes[pipe_num])
 
         iface = DirectMultiplexerInterface(applet, analyzer, self._registers,
-            self._fx2_arbiter, pipe_num, pins, pin_names, throttle)
+            self._fx2_arbiter, pipe_num, pins, throttle)
         self.submodules += iface
         return iface
 
 
 class DirectMultiplexerInterface(AccessMultiplexerInterface):
-    def __init__(self, applet, analyzer, registers, fx2_arbiter, pipe_num, pins, pin_names,
+    def __init__(self, applet, analyzer, registers, fx2_arbiter, pipe_num, pins,
                  throttle):
         assert throttle in ("full", "fifo", "none")
 
@@ -140,35 +138,26 @@ def __init__(self, applet, analyzer, registers, fx2_arbiter, pipe_num, pins, pin
         self._fx2_arbiter = fx2_arbiter
         self._pipe_num    = pipe_num
         self._pins        = pins
-        self._pin_names   = pin_names
-        self._used_pins   = set()
         self._throttle    = throttle
 
         self.reset, self._addr_reset = self._registers.add_rw(1, reset=1)
         self.logger.debug("adding reset register at address %#04x", self._addr_reset)
 
-    def get_pin_name(self, pin):
-        return self._pin_names[pin]
+    def get_pin_name(self, pin_num):
+        port, bit, req = self._pins[pin_num]
+        return "{}{}".format(port, bit)
 
-    def build_pin_tristate(self, pin, oe, o, i):
-        self._used_pins.add(pin)
+    def build_pin_tristate(self, pin_num, oe, o, i):
+        port, bit, req = self._pins[pin_num]
         self.specials += \
             Instance("SB_IO",
                 p_PIN_TYPE=C(0b101001, 6), # PIN_OUTPUT_TRISTATE|PIN_INPUT
-                io_PACKAGE_PIN=self._pins[pin],
+                io_PACKAGE_PIN=req(bit).io,
                 i_OUTPUT_ENABLE=oe,
                 i_D_OUT_0=o,
                 o_D_IN_0=i,
             )
 
-    def _build_pin_stub(self, pin):
-        self.specials += \
-            Instance("SB_IO",
-                p_PIN_TYPE=C(0b101001, 6), # PIN_OUTPUT_TRISTATE|PIN_INPUT
-                io_PACKAGE_PIN=self._pins[pin],
-                i_OUTPUT_ENABLE=0,
-            )
-
     def _throttle_fifo(self, fifo):
         self.submodules += fifo
         if self._throttle == "full":
@@ -208,8 +197,3 @@ def add_subtarget(self, subtarget):
 
         self.submodules += subtarget
         return subtarget
-
-    def do_finalize(self):
-        for pin in range(len(self._pins)):
-            if pin not in self._used_pins:
-                self._build_pin_stub(pin)
diff --git a/software/glasgow/platform/__init__.py b/software/glasgow/platform/__init__.py
@@ -8,8 +8,8 @@
 
 
 _io = [
-    ("clk_fx", 0, Pins("44"), IOStandard("LVCMOS33")),
-    ("clk_if", 0, Pins("20"), IOStandard("LVCMOS33")),
+    ("clk_fx", 0, Pins("44")),
+    ("clk_if", 0, Pins("20")),
 
     ("fx2", 0,
         Subsignal("sloe", Pins("6")),
@@ -19,20 +19,33 @@
         Subsignal("fifoadr", Pins("4 3")),
         Subsignal("flag", Pins("11 10 9 48")),
         Subsignal("fd", Pins("19 18 17 16 15 14 13 12")),
-        IOStandard("LVCMOS33")
     ),
 
-    ("io", 0, Pins("45 43 42 38 37 36 35 34"), IOStandard("LVCMOS33")),
-    ("io", 1, Pins("32 31 28 27 26 25 23 21"), IOStandard("LVCMOS33")),
+    ("port_a", 0, Subsignal("io", Pins("45"))),
+    ("port_a", 1, Subsignal("io", Pins("43"))),
+    ("port_a", 2, Subsignal("io", Pins("42"))),
+    ("port_a", 3, Subsignal("io", Pins("38"))),
+    ("port_a", 4, Subsignal("io", Pins("37"))),
+    ("port_a", 5, Subsignal("io", Pins("36"))),
+    ("port_a", 6, Subsignal("io", Pins("35"))),
+    ("port_a", 7, Subsignal("io", Pins("34"))),
+
+    ("port_b", 0, Subsignal("io", Pins("32"))),
+    ("port_b", 1, Subsignal("io", Pins("31"))),
+    ("port_b", 2, Subsignal("io", Pins("28"))),
+    ("port_b", 3, Subsignal("io", Pins("27"))),
+    ("port_b", 4, Subsignal("io", Pins("26"))),
+    ("port_b", 5, Subsignal("io", Pins("25"))),
+    ("port_b", 6, Subsignal("io", Pins("23"))),
+    ("port_b", 7, Subsignal("io", Pins("21"))),
 
     ("i2c", 0,
         Subsignal("scl", Pins("39")),
         Subsignal("sda", Pins("40")),
-        IOStandard("LVCMOS33")
     ),
 
     # open-drain
-    ("sync", 0, Pins("41"), IOStandard("LVCMOS33")),
+    ("sync", 0, Pins("41")),
 ]
 
 _connectors = [

diff --git a/software/glasgow/target/hardware.py b/software/glasgow/target/hardware.py
@@ -63,9 +63,8 @@ def __init__(self, multiplexer_cls=None, with_analyzer=False):
 
         if multiplexer_cls:
             ports = {
-                "A": lambda: self.platform.request("io", 0),
-                "B": lambda: self.platform.request("io", 1),
-                "S": lambda: self.platform.request("sync")
+                "A": (8, lambda n: self.platform.request("port_a", n)),
+                "B": (8, lambda n: self.platform.request("port_b", n)),
             }
             pipes = "PQ"
             self.submodules.multiplexer = multiplexer_cls(ports=ports, pipes=pipes,