whitequark · Feb 6, 2019 · Feb 6, 2019
Showing with 40 additions and 18 deletions.

+9 −4 software/glasgow/applet/__init__.py

+1 −7 software/glasgow/cli.py

+30 −7 software/glasgow/target/hardware.py
diff --git a/software/glasgow/applet/__init__.py b/software/glasgow/applet/__init__.py
@@ -83,6 +83,7 @@ async def run(self, args):
 from ..target.hardware import *
 from ..device.simulation import *
 from ..device.hardware import *
+from ..platform import GlasgowPlatformRevAB
 
 
 __all__ += ["GlasgowAppletTestCase", "synthesis_test", "applet_simulation_test",
@@ -184,7 +185,8 @@ def setUp(self):
 
     def assertBuilds(self, access="direct", args=[]):
         if access == "direct":
-            target = GlasgowHardwareTarget(multiplexer_cls=DirectMultiplexer)
+            target = GlasgowHardwareTarget(revision="A",
+                                           multiplexer_cls=DirectMultiplexer)
             access_args = DirectArguments(applet_name=self.applet.name,
                                           default_port="AB", pin_count=16)
         else:
@@ -222,14 +224,17 @@ async def run_simulated_applet(self):
     def _prepare_hardware_target(self, case, fixture, mode):
         assert mode in ("record", "replay")
 
-        self.target = GlasgowHardwareTarget(multiplexer_cls=DirectMultiplexer)
-        self.applet.build(self.target, self._parsed_args)
-
         if mode == "record":
             self.device = GlasgowHardwareDevice()
             self.device.demultiplexer = DirectDemultiplexer(self.device)
+            revision = self.device.revision
         else:
             self.device = None
+            revision = "A"
+
+        self.target = GlasgowHardwareTarget(revision=revision,
+                                            multiplexer_cls=DirectMultiplexer)
+        self.applet.build(self.target, self._parsed_args)
 
         self._recording = False
         self._recorders = []

diff --git a/software/glasgow/cli.py b/software/glasgow/cli.py
@@ -16,7 +16,6 @@
 from ._version import get_versions
 from .device import GlasgowDeviceError
 from .device.config import GlasgowConfig
-from .platform import GlasgowPlatformRevAB, GlasgowPlatformRevC
 from .target.hardware import GlasgowHardwareTarget
 from .gateware import GatewareBuildError
 from .gateware.analyzer import TraceDecoder
@@ -285,12 +284,7 @@ def serial(arg):
 
 # The name of this function appears in Verilog output, so keep it tidy.
 def _applet(revision, args):
-    platform_cls = {
-        "A": GlasgowPlatformRevAB,
-        "B": GlasgowPlatformRevAB,
-        "C": GlasgowPlatformRevC,
-    }
-    target = GlasgowHardwareTarget(platform_cls=platform_cls[revision],
+    target = GlasgowHardwareTarget(revision=revision,
                                    multiplexer_cls=DirectMultiplexer,
                                    with_analyzer=hasattr(args, "trace") and args.trace)
     applet = GlasgowApplet.all_applets[args.applet]()

diff --git a/software/glasgow/target/hardware.py b/software/glasgow/target/hardware.py
@@ -12,6 +12,7 @@
 from ..gateware.registers import I2CRegisters
 from ..gateware.fx2 import FX2Arbiter
 from ..gateware.platform.lattice import special_overrides
+from ..platform import GlasgowPlatformRevAB, GlasgowPlatformRevC
 from .analyzer import GlasgowAnalyzer
 
 
@@ -48,8 +49,15 @@ def __init__(self, platform):
 class GlasgowHardwareTarget(Module):
     sys_clk_freq = 30e6
 
-    def __init__(self, platform_cls, multiplexer_cls=None, with_analyzer=False):
-        self.platform = platform_cls()
+    def __init__(self, revision, multiplexer_cls=None, with_analyzer=False):
+        if revision == "A":
+            self.platform = GlasgowPlatformRevAB()
+        elif revision == "B":
+            self.platform = GlasgowPlatformRevAB()
+        elif revision == "C":
+            self.platform = GlasgowPlatformRevC()
+        else:
+            raise ValueError("Unknown revision")
 
         try:
             unused = self.platform.request("unused")
@@ -67,14 +75,17 @@ def __init__(self, platform_cls, multiplexer_cls=None, with_analyzer=False):
 
         self.submodules.fx2_arbiter = FX2Arbiter(self.platform.request("fx2"))
 
+        self.ports = {
+            "A": (8, lambda n: self.platform.request("port_a", n)),
+            "B": (8, lambda n: self.platform.request("port_b", n)),
+        }
+
         if multiplexer_cls:
-            ports = {
-                "A": (8, lambda n: self.platform.request("port_a", n)),
-                "B": (8, lambda n: self.platform.request("port_b", n)),
-            }
             pipes = "PQ"
-            self.submodules.multiplexer = multiplexer_cls(ports=ports, pipes=pipes,
+            self.submodules.multiplexer = multiplexer_cls(ports=self.ports, pipes="PQ",
                 registers=self.registers, fx2_arbiter=self.fx2_arbiter)
+        else:
+            self.multiplexer = None
 
         if with_analyzer:
             self.submodules.analyzer = GlasgowAnalyzer(self.registers, self.multiplexer)
@@ -87,6 +98,18 @@ def finalize(self, *args, **kwargs):
             if self.analyzer:
                 self.analyzer._finalize_pin_events()
 
+            unused_pins = []
+            for width, req in self.ports.values():
+                for n in range(width):
+                    try:
+                        unused_pins.append(req(n))
+                    except migen.build.generic_platform.ConstraintError:
+                        pass
+            for unused_pin in unused_pins:
+                self.specials += TSTriple().get_tristate(unused_pin.io)
+                if hasattr(unused_pin, "oe"):
+                    self.comb += unused_pin.oe.eq(0)
+
             super().finalize(*args, **kwargs)
 
     def get_fragment(self):