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Simulator: adding two clocks to a single domain causes DeadlineError in simulation #27

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q3k opened this issue Jan 26, 2019 · 0 comments

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@q3k
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q3k commented Jan 26, 2019

From IRC, when I run:

class PulseSynchronizerTestCase(FHDLTestCase):
    def test_basic(self):
        m = Module()
        m.domains += ClockDomain("one")
        m.domains += ClockDomain("two")
 
        with Simulator(m, vcd_file=open("test.vcd", "w")) as sim:
            sim.add_clock(2e-6, domain="one")
            sim.add_clock(3e-6, domain="one")
            def process():
                yield Tick(domain="one")
                yield Tick(domain="two")
            sim.add_process(process)
            sim.run()

The bug is sim.add_clock(3e-6, domain="one"), instead of domain="two". However, instead of a nice error, I get:

self = <nmigen.back.pysim.Simulator object at 0x7fb1836445f8>, run_passive = False

    def step(self, run_passive=False):
        # Are there any delta cycles we should run?
        if self._state.curr_dirty.any():
            # We might run some delta cycles, and we have simulator processes waiting on
            # a deadline. Take care to not exceed the closest deadline.
            if self._wait_deadline and \
                    (self._timestamp + self._delta) >= min(self._wait_deadline.values()):
                # Oops, we blew the deadline. We *could* run the processes now, but this is
                # virtually certainly a logic loop and a design bug, so bail out instead.d
>               raise DeadlineError("Delta cycles exceeded process deadline; combinatorial loop?")
E               nmigen.back.pysim.DeadlineError: Delta cycles exceeded process deadline; combinatorial loop?

nmigen/back/pysim.py:755: DeadlineError
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