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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 66466a8a0ec8
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  • 1 commit
  • 2 files changed
  • 1 contributor

Commits on Jan 18, 2019

  1. back.rtlil: only emit each AnyConst/AnySeq cell once.

    These are semantically like signals, not like constants.
    whitequark committed Jan 18, 2019
    Copy the full SHA
    66466a8 View commit details
Showing with 13 additions and 4 deletions.
  1. +9 −0 nmigen/back/rtlil.py
  2. +4 −4 nmigen/hdl/ast.py
9 changes: 9 additions & 0 deletions nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -227,6 +227,7 @@ def __init__(self, rtlil):
self.wires = ast.SignalDict()
self.driven = ast.SignalDict()
self.ports = ast.SignalDict()
self.anys = ast.ValueDict()

self.expansions = ast.ValueDict()

@@ -377,23 +378,31 @@ def on_Const(self, value):
return "{}'{:0{}b}".format(value.nbits, value_twos_compl, value.nbits)

def on_AnyConst(self, value):
if value in self.s.anys:
return self.s.anys[value]

res_bits, res_sign = value.shape()
res = self.s.rtlil.wire(width=res_bits)
self.s.rtlil.cell("$anyconst", ports={
"\\Y": res,
}, params={
"WIDTH": res_bits,
}, src=src(value.src_loc))
self.s.anys[value] = res
return res

def on_AnySeq(self, value):
if value in self.s.anys:
return self.s.anys[value]

res_bits, res_sign = value.shape()
res = self.s.rtlil.wire(width=res_bits)
self.s.rtlil.cell("$anyseq", ports={
"\\Y": res,
}, params={
"WIDTH": res_bits,
}, src=src(value.src_loc))
self.s.anys[value] = res
return res

def on_Signal(self, value):
8 changes: 4 additions & 4 deletions nmigen/hdl/ast.py
Original file line number Diff line number Diff line change
@@ -255,7 +255,7 @@ def __repr__(self):
C = Const # shorthand


class AnyValue(Value):
class AnyValue(Value, DUID):
def __init__(self, shape):
super().__init__(src_loc_at=0)
if isinstance(shape, int):
@@ -1119,7 +1119,7 @@ def __init__(self, value):
def __hash__(self):
if isinstance(self.value, Const):
return hash(self.value.value)
elif isinstance(self.value, Signal):
elif isinstance(self.value, (Signal, AnyValue)):
return hash(self.value.duid)
elif isinstance(self.value, (ClockSignal, ResetSignal)):
return hash(self.value.domain)
@@ -1149,7 +1149,7 @@ def __eq__(self, other):

if isinstance(self.value, Const):
return self.value.value == other.value.value
elif isinstance(self.value, Signal):
elif isinstance(self.value, (Signal, AnyValue)):
return self.value is other.value
elif isinstance(self.value, (ClockSignal, ResetSignal)):
return self.value.domain == other.value.domain
@@ -1191,7 +1191,7 @@ def __lt__(self, other):

if isinstance(self.value, Const):
return self.value < other.value
elif isinstance(self.value, Signal):
elif isinstance(self.value, (Signal, AnyValue)):
return self.value.duid < other.value.duid
elif isinstance(self.value, Slice):
return (ValueKey(self.value.value) < ValueKey(other.value.value) and