Lots of refactoring of ARM CoreSight classes

azonenberg · Jul 5, 2018 · 50ad5ef · 50ad5ef
1 parent a14a510
commit 50ad5ef
Show file tree

Hide file tree

Showing 11 changed files with 254 additions and 92 deletions.
diff --git a/ARMAPBDevice.h b/ARMAPBDevice.h
@@ -57,6 +57,7 @@ class ARMAPBDevice
 	// General device info
 
 	virtual std::string GetDescription() =0;
+	virtual void PrintInfo() =0;
 
 protected:
 

diff --git a/ARMCoreSightDevice.cpp b/ARMCoreSightDevice.cpp
@@ -0,0 +1,85 @@
+/***********************************************************************************************************************
+*                                                                                                                      *
+* ANTIKERNEL v0.1                                                                                                      *
+*                                                                                                                      *
+* Copyright (c) 2012-2018 Andrew D. Zonenberg                                                                          *
+* All rights reserved.                                                                                                 *
+*                                                                                                                      *
+* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the     *
+* following conditions are met:                                                                                        *
+*                                                                                                                      *
+*    * Redistributions of source code must retain the above copyright notice, this list of conditions, and the         *
+*      following disclaimer.                                                                                           *
+*                                                                                                                      *
+*    * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the       *
+*      following disclaimer in the documentation and/or other materials provided with the distribution.                *
+*                                                                                                                      *
+*    * Neither the name of the author nor the names of any contributors may be used to endorse or promote products     *
+*      derived from this software without specific prior written permission.                                           *
+*                                                                                                                      *
+* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   *
+* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
+* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES        *
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR       *
+* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE       *
+* POSSIBILITY OF SUCH DAMAGE.                                                                                          *
+*                                                                                                                      *
+***********************************************************************************************************************/
+
+/**
+	@file
+	@author Andrew D. Zonenberg
+	@brief Base class for ARM CoreSight components on a debug APB bus
+ */
+#include "jtaghal.h"
+#include "ARMAPBDevice.h"
+#include "ARMCoreSightDevice.h"
+
+using namespace std;
+
+ARMCoreSightDevice::ARMCoreSightDevice(ARMDebugMemAccessPort* ap, uint32_t address, ARMDebugPeripheralIDRegisterBits idreg)
+	: ARMAPBDevice(ap, address, idreg)
+{
+}
+
+ARMCoreSightDevice::~ARMCoreSightDevice()
+{
+}
+
+void ARMCoreSightDevice::PrintInfo()
+{
+	LogVerbose("%s rev %d.%d.%d\n",
+		GetDescription().c_str(),
+		m_idreg.revnum, m_idreg.cust_mod, m_idreg.revand);
+}
+
+string ARMCoreSightDevice::GetDescription()
+{
+	switch(m_idreg.partnum)
+	{
+		case 0x906:
+			return "CoreSight Cross Trigger Interface";
+		case 0x907:
+			return "CoreSight Embedded Trace Buffer";
+		case 0x908:
+			return "CoreSight Trace Funnel";
+		case 0x912:
+			return "CoreSight Trace Port Interface Unit";
+
+		//ID is 913, not 914. CoreSight Components TRM is wrong.
+		//See ARM #TAC650738
+		case 0x913:
+			return "CoreSight Instrumentation Trace Macrocell";
+		case 0x914:
+			return "CoreSight Serial Wire Output";
+		case 0x950:
+			return "Cortex-A9 Program Trace Macrocell";
+		case 0x9A0:
+			return "Cortex-A9 Performance Monitoring Unit";
+
+		default:
+			LogWarning("Unknown ARM device (part number 0x%x)\n", m_idreg.partnum);
+			return "unknown CoreSight device";
+	}
+}
diff --git a/ARMCoreSightDevice.h b/ARMCoreSightDevice.h
@@ -0,0 +1,49 @@
+/***********************************************************************************************************************
+*                                                                                                                      *
+* ANTIKERNEL v0.1                                                                                                      *
+*                                                                                                                      *
+* Copyright (c) 2012-2018 Andrew D. Zonenberg                                                                          *
+* All rights reserved.                                                                                                 *
+*                                                                                                                      *
+* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the     *
+* following conditions are met:                                                                                        *
+*                                                                                                                      *
+*    * Redistributions of source code must retain the above copyright notice, this list of conditions, and the         *
+*      following disclaimer.                                                                                           *
+*                                                                                                                      *
+*    * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the       *
+*      following disclaimer in the documentation and/or other materials provided with the distribution.                *
+*                                                                                                                      *
+*    * Neither the name of the author nor the names of any contributors may be used to endorse or promote products     *
+*      derived from this software without specific prior written permission.                                           *
+*                                                                                                                      *
+* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   *
+* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
+* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES        *
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR       *
+* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE       *
+* POSSIBILITY OF SUCH DAMAGE.                                                                                          *
+*                                                                                                                      *
+***********************************************************************************************************************/
+
+/**
+	@file
+	@author Andrew D. Zonenberg
+	@brief Base class for ARM CoreSight components (other than CPU cores) on a debug APB bus
+ */
+#ifndef ARMCoreSightDevice_h
+#define ARMCoreSightDevice_h
+
+class ARMCoreSightDevice : public ARMAPBDevice
+{
+public:
+	ARMCoreSightDevice(
+		ARMDebugMemAccessPort* ap, uint32_t address, ARMDebugPeripheralIDRegisterBits idreg);
+	virtual ~ARMCoreSightDevice();
+
+	virtual std::string GetDescription();
+	virtual void PrintInfo();
+};
+
+#endif
diff --git a/ARMCortexA9.cpp b/ARMCortexA9.cpp
@@ -49,35 +49,47 @@ using namespace std;
 ARMCortexA9::ARMCortexA9(ARMDebugMemAccessPort* ap, uint32_t address, ARMDebugPeripheralIDRegisterBits idreg)
 	: ARMAPBDevice(ap, address, idreg)
 {
-	LogDebug("Found ARM Cortex-A9 at %08x, probing...\n", address);
+	LogTrace("Found ARM Cortex-A9 at %08x, probing...\n", address);
 	LogIndenter li;
 
 	//Read the Debug ID register and extract flags
-	ARMv7DebugIDRegister did;
-	did.word = ReadRegisterByIndex(DBGDIDR);
-	m_breakpoints = did.bits.bpoints_minus_one + 1;
-	m_context_breakpoints = did.bits.context_bpoints_minus_one + 1;
-	m_watchpoints = did.bits.wpoints_minus_one + 1;
-	m_hasDevid = did.bits.has_dbgdevid;
-	m_hasSecExt = did.bits.sec_ext;
-	m_hasSecureHalt = did.bits.sec_ext && !did.bits.no_secure_halt;
-	m_revision = did.bits.revision;
-	m_variant = did.bits.variant;
-	if(did.bits.pcsr_legacy_addr)
+	m_deviceID.word = ReadRegisterByIndex(DBGDIDR);
+	m_breakpoints = m_deviceID.bits.bpoints_minus_one + 1;
+	m_context_breakpoints = m_deviceID.bits.context_bpoints_minus_one + 1;
+	m_watchpoints = m_deviceID.bits.wpoints_minus_one + 1;
+	m_hasDevid = m_deviceID.bits.has_dbgdevid;
+	m_hasSecExt = m_deviceID.bits.sec_ext;
+	m_hasSecureHalt = m_deviceID.bits.sec_ext && !m_deviceID.bits.no_secure_halt;
+	m_revision = m_deviceID.bits.revision;
+	m_variant = m_deviceID.bits.variant;
+	if(m_deviceID.bits.pcsr_legacy_addr)
 		m_pcsrIndex = DBGPCSR_LEGACY;
 	else
 		m_pcsrIndex = DBGPCSR;
 
-	//Print it out
-	PrintIDRegister(did);
-
 	//DBGDSMCR turn off MMU
 
 	//TODO: Write to DBGDRCR to halt the CPU (C11.11.17)
 
 	//TODO: Write to DBGDSCCR to force write-through cache (C11.11.19)
 
 	//DBGDEVID[3:0] 2226
+}
+
+ARMCortexA9::~ARMCortexA9()
+{
+
+}
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// General device info
+
+void ARMCortexA9::PrintInfo()
+{
+	LogVerbose("%s\n", GetDescription().c_str());
+	LogIndenter li;
+
+	PrintIDRegister(m_deviceID);
 
 	//Read DBGDSCR to get status stuff (TODO: make struct) for this
 	//uint32_t dbgdscr = ReadRegisterByIndex(DBGDSCR_EXT);
@@ -98,23 +110,14 @@ ARMCortexA9::ARMCortexA9(ARMDebugMemAccessPort* ap, uint32_t address, ARMDebugPe
 
 	//Read L0_SEL
 
-
 	//Read the PC and dump the instruction at that address
 	uint32_t pc = SampleProgramCounter();
-	LogDebug("PC = %08x\n", pc);
+	LogVerbose("PC = %08x\n", pc);
 	//uint32_t value = ReadMemory(0xE0000000);//m_ap->ReadWord(0x80000000); //ReadMemory(0xFC000000);
 
 	//LogDebug("    value = %08x\n", value);
 }
 
-ARMCortexA9::~ARMCortexA9()
-{
-
-}
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// General device info
-
 string ARMCortexA9::GetDescription()
 {
 	char tmp[128];
@@ -132,7 +135,7 @@ string ARMCortexA9::GetDescription()
 
 void ARMCortexA9::PrintIDRegister(ARMv7DebugIDRegister did)
 {
-	LogDebug("CPU rev %u variant %u\n", did.bits.revision, did.bits.variant);
+	LogVerbose("CPU rev %u variant %u\n", did.bits.revision, did.bits.variant);
 
 	const char* arches[]=
 	{
@@ -154,23 +157,23 @@ void ARMCortexA9::PrintIDRegister(ARMv7DebugIDRegister did)
 		"reserved f"
 	};
 
-	LogDebug("Arch %s\n", arches[did.bits.debug_arch_version]);
+	LogVerbose("Arch %s\n", arches[did.bits.debug_arch_version]);
 
 
 	if(did.bits.sec_ext)
 	{
-		LogDebug("Security extensions\n");
+		LogVerbose("Security extensions\n");
 		if(did.bits.sec_ext && did.bits.no_secure_halt)
 			LogDebug("    (but no secure halt)\n");
 	}
 	if(did.bits.pcsr_legacy_addr)
-		LogDebug("PCSR is at legacy address\n");
+		LogVerbose("PCSR is at legacy address\n");
 	if(did.bits.has_dbgdevid)
-		LogDebug("Has debug device ID\n");
+		LogVerbose("Has debug device ID\n");
 	//TODO: arch version
-	LogDebug("%d breakpoints (%d with context matching)\n",
+	LogVerbose("%d breakpoints (%d with context matching)\n",
 		did.bits.bpoints_minus_one+1, did.bits.context_bpoints_minus_one+1);
-	LogDebug("%d watchpoints\n", did.bits.wpoints_minus_one + 1);
+	LogVerbose("%d watchpoints\n", did.bits.wpoints_minus_one + 1);
 }
 
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

diff --git a/ARMCortexA9.h b/ARMCortexA9.h
@@ -192,7 +192,7 @@ union ARMv7DebugStatusControlRegister
 } __attribute__ ((packed));
 
 /**
-	@brief Generic base class for all debuggable devices (MCUs etc)
+	@brief An ARM Cortex-A9 CPU core, as seen over a CoreSight APB bus
 
 	\ingroup libjtaghal
  */
@@ -256,6 +256,7 @@ class ARMCortexA9 	: public DebuggableDevice
 	// General device info
 
 	virtual std::string GetDescription();
+	virtual void PrintInfo();
 
 	///Sample program counter (for sample-based profiling)
 	uint32_t SampleProgramCounter()
@@ -279,6 +280,8 @@ class ARMCortexA9 	: public DebuggableDevice
 	unsigned int m_variant;
 	//TODO: arch version
 
+	ARMv7DebugIDRegister m_deviceID;
+
 	///Device-dependent address of the program counter sample register (PCSR)
 	CORTEX_A9_DEBUG_REGISTERS m_pcsrIndex;
 };

diff --git a/ARMDebugAccessPort.h b/ARMDebugAccessPort.h
@@ -98,6 +98,9 @@ class ARMDebugAccessPort
 	dap_type GetBusType()
 	{ return m_daptype; }
 
+	unsigned int GetVersion()
+	{ return m_id.bits.revision; }
+
 	////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 	// General device info
 
@@ -109,6 +112,9 @@ class ARMDebugAccessPort
 	ARMDebugPort* GetDebugPort()
 	{ return m_dp; }
 
+	uint8_t GetAPNumber()
+	{ return m_apnum; }
+
 protected:
 	ARMDebugPort* m_dp;
 	uint8_t m_apnum;