Fixed handling of MEM-APs that default to non-word access size

azonenberg · Jul 10, 2018 · c617ea2 · c617ea2
1 parent 5601a0d
commit c617ea2
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Showing 2 changed files with 24 additions and 14 deletions.
diff --git a/ARMDebugMemAccessPort.cpp b/ARMDebugMemAccessPort.cpp
@@ -64,6 +64,14 @@ ARMDebugMemAccessPort::ARMDebugMemAccessPort(ARMDebugPort* dp, uint8_t apnum, AR
 			"Invalid DAP type",
 			"");
 	}
+
+	//If the access size is not 32-bit, make it 32-bit
+	ARMDebugMemAPControlStatusWord csw = GetStatusRegister();
+	if(csw.bits.size != ACCESS_WORD)
+	{
+		csw.bits.size = ACCESS_WORD;
+		m_dp->APRegisterWrite(m_apnum, ARMDebugPort::REG_MEM_CSW, csw.word);
+	}
 }
 
 void ARMDebugMemAccessPort::Initialize()
@@ -220,17 +228,11 @@ void ARMDebugMemAccessPort::LoadROMTable(uint32_t baseAddress)
 				"");
 		}
 
-		//TODO: support this
-		if(entry & 0x80000000)
-		{
-			throw JtagExceptionWrapper(
-				"Negative offsets from ROM table not implemented",
-				"");
-		}
-
 		//Calculate the actual address of this node
 		uint32_t offset = entry >> 12;
-		uint32_t address = (offset << 12) | baseAddress;
+		uint32_t address = (offset << 12) + baseAddress;
+		if(entry & 0x80000000)
+			address = baseAddress - (~(offset << 12) + 1);
 
 		//Walk this table entry
 		uint32_t compid_raw[4];
@@ -245,9 +247,9 @@ void ARMDebugMemAccessPort::LoadROMTable(uint32_t baseAddress)
 		//Verify the mandatory component ID bits are in the right spots
 		if( (compid & 0xffff0fff) != (0xb105000d) )
 		{
-			throw JtagExceptionWrapper(
-				"Invalid ROM table ID (wrong preamble)",
-				"");
+			LogError("Invalid ROM table ID (wrong preamble), got %08x and expected something close to 0xb105000d\n",
+				compid);
+			continue;
 		}
 
 		//Figure out what it means
@@ -260,6 +262,11 @@ void ARMDebugMemAccessPort::LoadROMTable(uint32_t baseAddress)
 				ProcessDebugBlock(address);
 				break;
 
+			//Process "generic IP" blocks (ignore them)
+			case CLASS_GENERIC_IP:
+				LogTrace("Found generic IP block at %08x, ignoring\n", address);
+				break;
+
 			//Additional ROM table
 			case CLASS_ROMTABLE:
 				{
@@ -364,6 +371,7 @@ void ARMDebugMemAccessPort::ProcessDebugBlock(uint32_t base_address)
 			//Unknown
 			default:
 			{
+				LogDebug("Unknown CoreSight device\n");
 				ARMCoreSightDevice* dev = new ARMCoreSightDevice(this, base_address, reg.bits);
 				m_debugDevices.push_back(dev);
 			}

diff --git a/ARMDebugMemAccessPort.h b/ARMDebugMemAccessPort.h
@@ -121,10 +121,12 @@ class ARMDebugMemAccessPort : public ARMDebugAccessPort
 		ACCESS_INVALID	= 3,
 	};
 
+	//ADI spec table 9-3
 	enum ComponentClass
 	{
-		CLASS_ROMTABLE = 1,
-		CLASS_CORESIGHT	= 9
+		CLASS_ROMTABLE 		= 0x1,
+		CLASS_CORESIGHT		= 0x9,
+		CLASS_GENERIC_IP	= 0xe
 	};
 
 	virtual void PrintStatusRegister();