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SystemVerilog parser using Tree-Sitter #44

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drom opened this issue Mar 23, 2020 · 0 comments

drom commented Mar 23, 2020 •

edited

🚧 Work In Progress 🚧

Brief explanation

Verilog / SystemVerilog is a major hardware description language used in FPGA and Chip design.
Tree-Sitter is an incremental parsing system for programming tools https://tree-sitter.github.io
https://github.com/tree-sitter/tree-sitter-verilog - is IEEE 1800-2017 compliant parser.
Included in SymbiFlow SystemVerilog test suit: https://symbiflow.github.io/sv-tests/
Used in Atom editor: https://github.blog/2018-10-31-atoms-new-parsing-system/
Via plugin: https://github.com/drom/atom-ide-eda

Detailed Explanation

https://github.com/tree-sitter/tree-sitter-verilog/issues

Further reading

🚧 Work In Progress 🚧

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