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vendor.xilinx_7series: Vivado TIMING-2 Warning #301
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Can you explain what does the filter expression in your commit does? |
@whitequark this is indeed ugly and should be fixed, it's purpose is to filter negative ports of differential clock inputs, ending with |
You did explain why it's ugly, which is helpful (thanks!). Unfortunately, you didn't explain what it does, so I can't help you work out a nicer replacement. I don't have the Xilinx flavor of Tcl API memorized. |
Here's an excerpt from UG906 explaining the TIMING-2 warning and how to use The Tcl fragment does exactly that, it starts from the clock signal and determines it's startpoint using [filter -regexp [all_fanin -flat -startpoints_only \
[get_nets {{signal|hierarchy("/")}}]] {NAME =~{(^.*__p$)|(^.*__io$)|(^.+/.+$)}}] Vivado Tcl reference is available here: Tcl Command Reference Guide, UG835. |
This can expose important timing issues, such as m-labs#301.
Vivado issues TIMING-2 (default severity: CRITICAL) when
create_clock
uses a signal.Here is a potential solution to please
create_clock
: peteut@9e79a30 .The text was updated successfully, but these errors were encountered: