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base repository: m-labs/nmigen
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compare: 8184efd61215
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Jan 9, 2020

  1. vendor.intel: fix output enable width for XDR=0 case.

    Fixes #297.
    schwigi authored and whitequark committed Jan 9, 2020
    Copy the full SHA
    8184efd View commit details
Showing with 3 additions and 2 deletions.
  1. +3 −2 nmigen/vendor/intel.py
5 changes: 3 additions & 2 deletions nmigen/vendor/intel.py
Original file line number Diff line number Diff line change
@@ -221,8 +221,9 @@ def get_oneg(o):

@staticmethod
def _get_oereg(m, pin):
# altiobuf_ requires an output enable signal for each pin, but pin.oe is 1 bit wide.
if pin.xdr == 0:
return pin.oe
return Repl(pin.oe, pin.width)
elif pin.xdr in (1, 2):
oe_reg = Signal(pin.width, name="{}_oe_reg".format(pin.name))
oe_reg.attrs["useioff"] = "1"
@@ -283,7 +284,7 @@ def get_tristate(self, pin, port, attrs, invert):
p_use_oe="TRUE",
i_datain=self._get_oreg(m, pin, invert),
o_dataout=port,
i_oe=pin.oe,
i_oe=self._get_oereg(m, pin)
)
return m