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base repository: GlasgowEmbedded/glasgow
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base: 1fe537e565ea
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head repository: GlasgowEmbedded/glasgow
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compare: 4d745342d0bd
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Jan 25, 2020

  1. applet.radio.nrf24l01: flush RX FIFO before receiving.

    Otherwise packets could get stuck in it.
    
    Also, flush FIFOs before enabling TX/RX, to avoid a race condition.
    whitequark committed Jan 25, 2020
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    006d172 View commit details
  2. vendor: update libfx2.

    whitequark committed Jan 25, 2020
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    4d74534 View commit details
Showing with 13 additions and 3 deletions.
  1. +12 −2 software/glasgow/applet/radio/nrf24l01/__init__.py
  2. +1 −1 vendor/libfx2
14 changes: 12 additions & 2 deletions software/glasgow/applet/radio/nrf24l01/__init__.py
Original file line number Diff line number Diff line change
@@ -296,6 +296,9 @@ async def interact(self, device, args, nrf24l01_iface):
en_dpl = args.dynamic_length
en_dyn_ack = hasattr(args, "no_ack") and args.no_ack

await nrf24l01_iface.write_register(ADDR_CONFIG,
REG_CONFIG(PWR_UP=0).to_int())

feature = REG_FEATURE(EN_DPL=en_dpl, EN_DYN_ACK=en_dyn_ack).to_int()
await nrf24l01_iface.write_register(ADDR_FEATURE, feature)
if (await nrf24l01_iface.read_register(ADDR_FEATURE)) != feature:
@@ -329,15 +332,15 @@ async def interact(self, device, args, nrf24l01_iface):
if en_dpl:
await nrf24l01_iface.write_register(ADDR_DYNPD,
REG_DYNPD(DPL_P0=1).to_int())
await nrf24l01_iface.write_register(ADDR_CONFIG,
REG_CONFIG(PRIM_RX=0, PWR_UP=1, CRCO=crco, EN_CRC=en_crc).to_int())

while True:
fifo_status = REG_FIFO_STATUS.from_int(
await nrf24l01_iface.read_register(ADDR_FIFO_STATUS))
if fifo_status.TX_EMPTY:
break
await nrf24l01_iface.flush_tx()
await nrf24l01_iface.write_register(ADDR_CONFIG,
REG_CONFIG(PRIM_RX=0, PWR_UP=1, CRCO=crco, EN_CRC=en_crc).to_int())

await nrf24l01_iface.write_tx_payload(args.payload,
ack=not args.compat_framing and not args.no_ack)
@@ -391,6 +394,13 @@ async def interact(self, device, args, nrf24l01_iface):
raise RadioNRF24L01Error(
"One of --dynamic-length or --length must be specified")
await nrf24l01_iface.write_register(ADDR_RX_PW_Pn(0), args.length)

while True:
fifo_status = REG_FIFO_STATUS.from_int(
await nrf24l01_iface.read_register(ADDR_FIFO_STATUS))
if fifo_status.RX_EMPTY:
break
await nrf24l01_iface.flush_rx()
await nrf24l01_iface.write_register(ADDR_CONFIG,
REG_CONFIG(PRIM_RX=1, PWR_UP=1, CRCO=crco, EN_CRC=en_crc).to_int())

2 changes: 1 addition & 1 deletion vendor/libfx2