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Branch: Quicklogic : Yosys optimizes the design completely #63

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rakeshm75 opened this issue Mar 9, 2020 · 2 comments
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Branch: Quicklogic : Yosys optimizes the design completely #63

rakeshm75 opened this issue Mar 9, 2020 · 2 comments
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@glatosinski

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@rakeshm75
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Steps to reproduce the issue

  1. Synthesize the attached design using yosys
  2. Convert Yosys EDIF file to SpDE complaint format
    Yosys completely optimizes the design but when we enable the debug pins then it synthesizes the design correctly.
  3. Un-comment //`define USE_DEBUG_PORT in the AL4S3B_FPGA_Top.v file, we are enabling the debug pins
  4. Synthesize the attached design using yosys
    Now Yosys synthesizes the design correctly.

Attached the design.
Test_Design3.zip
@glatosinski glatosinski self-assigned this Mar 11, 2020
@glatosinski
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glatosinski commented Mar 12, 2020 •
edited by unfurl-links bot

I updated https://github.com/antmicro/yosys/tree/quicklogic fork, where the support for QuickLogic devices currently resides. Now the qlal4s3b_cell_macro module has attribute keep that will preserve this cell, and communication with it.

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@glatosinski glatosinski mentioned this issue Mar 12, 2020
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@rakeshm75
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The issue is fixed. So closing the issue.

Thanks & Best Regards,
Rakesh

@rakeshm75 rakeshm75 mentioned this issue Apr 14, 2020
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@glatosinski @rakeshm75