Steps to reproduce the issue

1. Synthesize the attached design using yosys
2. Convert Yosys EDIF file to SpDE complaint format
3. Load the design in SpDE
4. SpDE throws up the errors

This design is using both the RAM's and FIFO's. The EDF generated by Yosys has missing FIFO ports in the RAM/ FIFO definition (ram8k_2x1_cell_macro). The following ports are missing:
1. Almost_Empty
2. Almost_Full
3. PUSH_FLAG
4. POP_FLAG
I have attached the design here (rtl and edf).
Test_Design_1.zip