Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: amaranth-lang/amaranth
base: 814ffde6fbf3
Choose a base ref
...
head repository: amaranth-lang/amaranth
compare: 792f35ac8fed
Choose a head ref
  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Apr 13, 2020

  1. back.rtlil: refuse to create extremely large wires. 

    Such wires are likely to trigger pathological behavior in Yosys and,
if applicable, other toolchains that consume Verilog converted from
RTLIL.

Fixes #341.
    @whitequark
    whitequark committed Apr 13, 2020
    Copy the full SHA
    792f35a View commit details
    Browse the repository at this point in the history