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Simulation of module with undriven signal causes generated VCD to not contain the signal, but contain an individual signal for each character of the undriven signal's name #345

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the6p4c opened this issue Apr 1, 2020 · 2 comments
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Simulation of module with undriven signal causes generated VCD to not contain the signal, but contain an individual signal for each character of the undriven signal's name #345

the6p4c opened this issue Apr 1, 2020 · 2 comments
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bug simulator:pysim
Milestone
0.3

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@the6p4c
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the6p4c commented Apr 1, 2020

This snippet illustrates the issue:

from nmigen import *
from nmigen.back import pysim

class Bug(Elaboratable):
    def __init__(self):
        self.reg = Signal()
        self.out = Signal()

    def elaborate(self, platform):
        m = Module()
        m.d.sync += self.out.eq(~self.out)

        # driving the signal fixes the issue
        # uncomment: vcd will be correct
        # m.d.comb += self.reg.eq(0)

        return m

bug = Bug()
fragment = Fragment.get(bug, None)
sim = pysim.Simulator(fragment)
sim.add_clock(1e-6)
with sim.write_vcd(vcd_file='bug.vcd', traces=[bug.out, bug.reg]):
    sim.run_until(1e-6 * 10, run_passive=True)

With the line driving reg inside elaborate commented out, the generated VCD starts:

$comment Generated by nMigen $end
$date 2020-04-01 22:07:22.464464 $end
$timescale 100 ps $end
$var wire 1 3 r $end
$var wire 1 4 e $end
$var wire 1 5 g $end
$scope module top $end
$var wire 1 0 clk $end
$var wire 1 1 rst $end
$var wire 1 2 out $end
$upscope $end
$enddefinitions $end

i.e. reg has somehow become three signals, r, e and g.

Driving reg combinatorically or with registered logic fixes the signal's name and value in the VCD.
@the6p4c
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the6p4c commented Apr 1, 2020

Experimenting, it appears this happens if the signal is unused in any way - either undriven, or not part of the module's logic.

@whitequark
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Ouch, I think I made a mistake fixing #280.

@whitequark whitequark added this to the 0.3 milestone Apr 3, 2020
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bug simulator:pysim
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0.3
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@whitequark @the6p4c