Update submodules and modernize platforms/target files #348

mateusz-holenko · 2020-02-26T12:11:05Z

This updates submodules, including LiteX, to the newer versions and fixes compatibility problems.

EDIT: This also includes rebased (and a bit reworked) changes from #311.

0001-emulator-Use-external-hw-common.h-from-LiteX.patch

targets/arty/base.py

scripts/build-linux.sh

mithro

Can you merge this with #311 ?

mateusz-holenko · 2020-02-28T12:42:25Z

Can you merge this with #311 ?

Do you mean you don't want to merge this branch itself, but together with #311 OR that this will be merged first and #311 should be rebased on top of this?

0b923aa in LiteX changes the way vendor tools are located and removes toolchain_path argument

Now that the target Makefile is included *before* the IMAGE_FILE is redefined, if FIRMWARE has been changed we will be using an old version of IMAGE_FILE from the environment, and thus were inadvertently generating two rules to build the "none" firmware bundle if FIRMWARE=none.

(Instead of relying on third_party/ports/fupy having a cached copy of the "hw" includes, which could get out of date; and was out of date after updating litex; modern litex has a different set of CSR routines.)

The new fork containt a commit removing an outdated `hw` directory generated by LiteX.

mateusz-holenko · 2020-04-04T12:29:55Z

@ewenmcneill - I cherry-picked more commits from you branch. Will you have some spare time to test the current version of this branch on the HW?
You mentioned that you have an access to TinyFPGA BX, right?

I'm currently testing it on Arty - I do that by simply running:

the default HDMI2USB firmware on lm32,
Micropython on vexriscv,
Zephyr on vexrsicv
and observing if it boots correctly and responds to an input on uart.

ewenmcneill · 2020-04-05T21:43:32Z

You mentioned that you have an access to TinyFPGA BX, right?

@mateusz-holenko Yes, I have a TinyFPGA BX among other devices. I was testing with TinyFPGA BX mostly because it was convenient and tiny to use for "laptop" development :-)

Seems to me like it's working. With the steps below to build PR #348, I get basically the same results as I was getting with my changes (compare, eg, with #277 (comment)).

git fetch origin pull/348/head:pr348
git checkout pr348
git submodule update --init --recursive
scripts/download-env.sh
make clean
make gateware
scripts/build-micropython.sh
make image-flash

gives me a working litex BIOS, with 10kB of RAM, and a working MicroPython.

I notice that you're temporarily pinned to my MicroPython WIP change. Possibly we should merge that into the FuPy MicroPython if we're agreed that's the direction we want to go? Then you could change the pin back to the FuPy one.

Ewen

(LX P=tinyfpga_bx.minimal F=micropython R=pr348) ewen@parthenon:/src/fpga/litex-
buildenv$ make firmware-connect
flterm --port=/dev/ttyUSB0 --speed=115200
[FLTERM] v2.4-29-g47d3b15 Starting...

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Apr  6 2020 09:27:48
 BIOS CRC passed (931d7dc5)

 Migen git sha1: 3f9809b
 LiteX git sha1: 536ae0e6

--=============== SoC ==================--
CPU:       LM32 @ 16MHz
ROM:       32KB
SRAM:      10KB

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
Booting from flash...
Executing booted program at 0x20058008

--============= Liftoff! ===============--
MicroPython v1.9.4-1430-ge23216bf2 on 2020-04-06; litex with lm32
>>> print("Hello World!")
Hello World!
>>>

(LX P=tinyfpga_bx.minimal F=micropython R=pr348) ewen@parthenon:/src/fpga/litex-
buildenv$ git log -2
commit 421a402a68824dda81395c58675c1d55c21a0261 (HEAD -> pr348)
Author: Mateusz Holenko <mholenko@antmicro.com>
Date:   Fri Apr 3 11:02:18 2020 +0200

    micropython: temporarily change the fork
    
    The new fork containt a commit removing an outdated `hw`
    directory generated by LiteX.

commit d9d9cf24393e5ea39808d25fb33a693ebdc7cbe4
Author: Ewen McNeill <ewen@naos.co.nz>
Date:   Fri Mar 13 22:19:22 2020 +1300

    micropython: link to litex hw includes
    
    (Instead of relying on third_party/ports/fupy having a cached copy of the
    "hw" includes, which could get out of date; and was out of date after updating
    litex; modern litex has a different set of CSR routines.)
(LX P=tinyfpga_bx.minimal F=micropython R=pr348) ewen@parthenon:/src/fpga/litex-
buildenv$

mithro · 2020-04-06T00:23:45Z

@ewenmcneill - Any idea if the ROM is coming from SPI flash? (I guess we should also put the ROM source in the BIOS output?)

ewenmcneill · 2020-04-06T00:29:52Z

@ewenmcneill - Any idea if the ROM is coming from SPI flash? (I guess we should also put the ROM source in the BIOS output?)

@mithro I can't see how the TinyFPGA rom segment wouldn't be coming from the SPI flash, given

litex-buildenv/targets/tinyfpga_bx/base.py

Lines 36 to 39 in 421a402

    
           # We save the ROM size passed in as the BIOS size, and then force the 
        
           # integrated ROM size to 0 to avoid integrated ROM.  
        
           bios_size = kwargs['integrated_rom_size'] 
        
           kwargs['integrated_rom_size'] = 0x0

and

litex-buildenv/targets/tinyfpga_bx/base.py

Lines 68 to 73 in 421a402

    
           self.add_constant("ROM_DISABLE", 1) 
        
           self.add_memory_region( 
        
               "rom", kwargs['cpu_reset_address'], bios_size, 
        
               type="cached+linker") 
        
           self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size+bios_size+platform.bootloader_size 
        
           self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)

It was definitely coming from the SPI Flash in the version I was working on, because I looked at the linker maps.

Ewen

ETA 2020-04-06 now that I've grabbed the laptop I built on, this is the TinyFPGA BX linker map:

(LX P=tinyfpga_bx.minimal F=micropython R=pr348) ewen@parthenon:/src/fpga/litex-
buildenv$ cat build/tinyfpga_bx_base_lm32.minimal/software/include/generated/regions.ld 
MEMORY {
	sram : ORIGIN = 0x01000000, LENGTH = 0x00002800
	csr : ORIGIN = 0x82000000, LENGTH = 0x00010000
	spiflash : ORIGIN = 0x20000000, LENGTH = 0x00100000
	rom : ORIGIN = 0x20050000, LENGTH = 0x00008000
	user_flash : ORIGIN = 0x20058000, LENGTH = 0x000a7f00
}
(LX P=tinyfpga_bx.minimal F=micropython R=pr348) ewen@parthenon:/src/fpga/litex-
buildenv$

Note how the rom segment overlaps the spiflash segment, and is immediately before the user_flash segment.

Also FWIW, MicroPython boots just as slowly as it did before, ie, consistent with slow SPI single speed no cache :-)

mithro · 2020-04-06T03:01:26Z

@ewenmcneill - Great! Just wanted to check. @mateusz-holenko Is this ready to merge now then?

mateusz-holenko · 2020-04-06T06:37:41Z

@mithro I tested it on Arty and both the default HDMI2USB and Micropython boot fine.
I was planning to test it today also on Nexys Video and netv2.

Otherwise I believe it's ready to be merged.

mateusz-holenko · 2020-04-06T06:40:20Z

I notice that you're temporarily pinned to my MicroPython WIP change. Possibly we should merge that into the FuPy MicroPython if we're agreed that's the direction we want to go? Then you could change the pin back to the FuPy one.

@ewenmcneill That was exactly my idea. Could you create a PR to FuPy MicroPython? Once it's merged I will point back to the original repository.

mateusz-holenko · 2020-04-06T06:42:29Z

@mithro Travis is red, but it's caused by some network problems when downloading conda packages:

('Connection broken: OSError("(104, \'ECONNRESET\')")', OSError("(104, 'ECONNRESET')"))

It happens a lot lately :(

All other tests passed.

mateusz-holenko · 2020-04-06T12:09:12Z

Tested on nexys_video and netv2 - the default firmware boots nicely to prompt.

The only problem was that for nexys_video I had to disable CAS module as there were errors during synthesis because user_btn5 and cpu_reset signals are using the same pin.

Targets tested on HW:

arty
nexys_video
netv2
tinyfpga_bx

mithro · 2020-04-06T15:38:30Z

Great! Let's merge for now and continue with more pull requests.

ewenmcneill · 2020-04-07T04:25:14Z

@ewenmcneill That was exactly my idea. Could you create a PR to FuPy MicroPython? Once it's merged I will point back to the original repository.

fupy/micropython#58, which I've just merged since I have commit rights on that repo, and since we all seem in agreement with the approach.

We'll want to revert 421a402 (which changes it to use my fork/branch) fairly soon. @mateusz-holenko Do you want do do that revert? Or should I create a revert commit/PR? (The two are currently the same, other than the merge commit in the FuPy MicroPython version.)

Ewen

mateusz-holenko · 2020-04-07T08:03:01Z

@mithro Great!

@ewenmcneill I created a PR: #385

probot-autolabeler bot added board-arty board-atlys board-basys3 board-cmod_a7 board-galatea board-ice40_hx8k_b_env board-mimasv2 board-minispartan6 board-neso board-netv2 board-opsis boards-artix7 boards-ice40 boards-spartan6 hdmi2*** hdmi2ethernet hdmi2usb level-infrastructure labels Feb 26, 2020

mateusz-holenko commented Feb 26, 2020

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0001-emulator-Use-external-hw-common.h-from-LiteX.patch Outdated Show resolved Hide resolved

mateusz-holenko commented Feb 26, 2020

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This was referenced Feb 26, 2020

Allow to boot Linux from flash #340

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Testing firmware in Renode on Travis #339

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mithro reviewed Feb 26, 2020

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mateusz-holenko force-pushed the update_submodules branch from 8e3b6ec to 3675714 Compare February 28, 2020 12:44

mateusz-holenko mentioned this pull request Mar 4, 2020

Increase in BIOS+firmware size increase with latest LiteX revision enjoy-digital/litex#371

Closed

mateusz-holenko force-pushed the update_submodules branch 2 times, most recently from c2d154f to 8e9db79 Compare March 6, 2020 09:58

probot-autolabeler bot added the firmware-fpga label Mar 6, 2020

mithro and others added 8 commits April 4, 2020 13:36

sim: Cleanup and modernize.

a304465

matrix_voice: Cleanup and modernize.

6962baf

sim: Add a fixme comment

6d8fc4e

scripts: add Vivado to PATH

f30dcd1

0b923aa in LiteX changes the way vendor tools are located and removes toolchain_path argument

test: fix imports of RemoteClient

243c1a7

make.py: region's (now) have a size, not a length

e7355c0

micropython: link to litex hw includes

d9d9cf2

(Instead of relying on third_party/ports/fupy having a cached copy of the "hw" includes, which could get out of date; and was out of date after updating litex; modern litex has a different set of CSR routines.)

mateusz-holenko force-pushed the update_submodules branch from 47b85f5 to 012c5f7 Compare April 4, 2020 11:37

micropython: temporarily change the fork

421a402

The new fork containt a commit removing an outdated `hw` directory generated by LiteX.

mateusz-holenko force-pushed the update_submodules branch from 012c5f7 to 421a402 Compare April 4, 2020 12:14

nexys_video: disable CAS as it conclicts with cpu_reset

9bcc7d0

mithro merged commit 2716c32 into timvideos:master Apr 6, 2020

ewenmcneill mentioned this pull request Apr 7, 2020

ports/fupy: Remove hw includes (use litex upstream) fupy/micropython#58

Merged

This was referenced Apr 7, 2020

Update litex submodule (currently 2019-11-18) #366

Closed

Ice40 HX8K EVB issues #277

Open

Cleanup (and fix) the ice40_hx8k_b_env target #384

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mateusz-holenko mentioned this pull request Jul 6, 2020

WIP -- Modernize platforms + target files #311

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Update submodules and modernize platforms/target files #348

Update submodules and modernize platforms/target files #348

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Update submodules and modernize platforms/target files #348

Update submodules and modernize platforms/target files #348

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