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base repository: whitequark/yosys
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  • 17 commits
  • 24 files changed
  • 4 contributors

Commits on Feb 6, 2020

  1. write_verilog: dump $mem cell attributes. 

    The Verilog backend already dumps attributes on RTLIL::Memory objects
but not on `$mem` cells.
    @whitequark
    whitequark committed Feb 6, 2020
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  2. edif: more resilience to mismatched port connection sizes. 

    Fixes YosysHQ#1653.
    @wanda-phi
    wanda-phi committed Feb 6, 2020
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    8f559b0 View commit details

  3. Fix/cleanup +/xilinx/arith_map.v

    @eddiehung
    eddiehung committed Feb 6, 2020
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  4. Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk

    @eddiehung
    eddiehung committed Feb 6, 2020
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    d625e39 View commit details

  5. Removing cells_sim.v from bram techmap pass

    Diego H committed Feb 6, 2020
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  6. Merge pull request YosysHQ#1684 from YosysHQ/eddie/xilinx_arith_map 

    Fix/cleanup +/xilinx/arith_map.v
    @eddiehung
    eddiehung authored Feb 6, 2020
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Commits on Feb 7, 2020

  1. xilinx: Add support for Spartan 3A DSP block RAMs. 

    Part of YosysHQ#1550
    @wanda-phi
    wanda-phi committed Feb 7, 2020
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  2. xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.

    @wanda-phi
    wanda-phi committed Feb 7, 2020
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  3. Merge pull request YosysHQ#1683 from whitequark/write_verilog-memattrs 

    write_verilog: dump $mem cell attributes
    @whitequark
    whitequark authored Feb 7, 2020
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  4. Merge pull request YosysHQ#1685 from dh73/gowin 

    Removing cells_sim from GoWin bram techmap
    @eddiehung
    eddiehung authored Feb 7, 2020
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  5. xilinx: Initial support for LUT4 devices. 

    Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.

Fixes YosysHQ#1547
    @wanda-phi
    wanda-phi committed Feb 7, 2020
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  6. xilinx: Add support for LUT RAM on LUT4-based devices. 

    There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.

Fixes YosysHQ#1549
    @wanda-phi
    wanda-phi committed Feb 7, 2020
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  7. Fix misc.abc9.abc9_abc9_luts

    @eddiehung
    eddiehung committed Feb 7, 2020
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  8. techmap: fix shiftx2mux decomposition

    @eddiehung
    eddiehung committed Feb 7, 2020
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  9. Merge pull request YosysHQ#1687 from YosysHQ/eddie/fix_ystests 

    Fix shiftx2mux, fix yosys-tests
    @eddiehung
    eddiehung authored Feb 7, 2020
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  10. Remove unnecessary comma

    @eddiehung
    eddiehung committed Feb 7, 2020
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Commits on Feb 9, 2020

  1. write_verilog: dump zero width sigspecs correctly. 

    See commit 4ff44d8 for details.
    @whitequark
    whitequark committed Feb 9, 2020
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