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Render LUT diagram #42

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drom opened this issue Mar 17, 2020 · 1 comment
Open

Render LUT diagram #42

drom opened this issue Mar 17, 2020 · 1 comment

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@drom
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drom commented Mar 17, 2020

Brief explanation

Render FPGA LUTs as a digital circuit diagram.

Detailed Explanation

FPGA devices use look-up table (LUT) to implement arbitrary combinatorial logic.

for N bit LUT configuration can be represented as an 2^N long number.

Most typical LUTs are LUT4 with N = 4 with 2^N = 16 bit config word shown on the figure below.

Mux representation of LUT is not the most human-readable one.

Any configuration of the LUT can be rendered as a digital circuit diagram.

https://github.com/drom/icedrom -- is an JavaScript libratry that can render LUT config as digital circuit diagram.

Read more HERE https://observablehq.com/@drom/lut4-decoder

@mithro mithro changed the title render LUT diagram Render LUT diagram Mar 18, 2020
@mithro
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mithro commented Mar 18, 2020

This would be excellent to be part of a sphinx extension - potentially http://sphinxcontrib-verilog-diagrams.rtfd.io/ too

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