Proposed solution to ResetSynchronizer redundancy.

amaranth-lang · Mar 5, 2020 · 0b75029 · whitequark · Mar 5, 2020 · 0b75029
1 parent e8f8998
commit 0b75029
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Showing 2 changed files with 13 additions and 7 deletions.
diff --git a/nmigen/lib/cdc.py b/nmigen/lib/cdc.py
@@ -125,13 +125,15 @@ class ResetSynchronizer(Elaboratable):
     Define the ``get_reset_sync`` platform method to override the implementation of
     :class:`ResetSynchronizer`, e.g. to instantiate library cells directly.
     """
-    def __init__(self, arst, *, domain="sync", stages=2, max_input_delay=None):
+    def __init__(self, arst, *, domain="sync", stages=2, max_input_delay=None, reset_less=False):
         _check_stages(stages)
 
         self.arst = arst
+        self.rst = Signal()
 
         self._domain = domain
         self._stages = stages
+        self._reset_less = reset_less
 
         self._max_input_delay = None
 
@@ -150,11 +152,18 @@ def elaborate(self, platform):
                  for index in range(self._stages)]
         for i, o in zip((0, *flops), flops):
             m.d.reset_sync += o.eq(i)
+
         m.d.comb += [
             ClockSignal("reset_sync").eq(ClockSignal(self._domain)),
             ResetSignal("reset_sync").eq(self.arst),
-            ResetSignal(self._domain).eq(flops[-1])
+            self.rst.eq(ResetSignal(self._domain))
         ]
+
+        if not self._reset_less:
+            m.d.comb += [
+                ResetSignal(self._domain).eq(flops[-1]),
+            ]
+
         return m
 
 

diff --git a/nmigen/lib/fifo.py b/nmigen/lib/fifo.py
@@ -373,13 +373,10 @@ def elaborate(self, platform):
         r_rst = Signal()
 
         # Create clock domain for ResetSynchronizer
-        rst_domain = ClockDomain(name="rst_cdc", async_reset=True, local=True)
-        m.domains += rst_domain
         rst_cdc = m.submodules.rst_cdc = \
-                ResetSynchronizer(w_rst, domain = "rst_cdc")
+            ResetSynchronizer(w_rst, domain=self._r_domain, reset_less=True)
         m.d.comb += [
-                rst_domain.clk.eq(ClockSignal(domain = self._r_domain)),
-                r_rst.eq(ResetSignal(domain = "rst_cdc")),
+            r_rst.eq(rst_cdc.rst),
         ]
 
         # Decode Gray code counter synchronized from write domain to overwrite binary