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Imagine you create a module of type M68000. It has a submodule of type BusAccess. To get a meaningful name in the rtlil and every tool that uses it, it is created in the recommended way in elaborate:
m.submodules.busaccess = busaccess = BusAccess()
Then the name "busaccess" is used, which is good. But it seems that module names must be unique in the whole system. So does that mean one couldn't have two instances of M68000 in the same system if we want significant names?
The text was updated successfully, but these errors were encountered:
I may have missed something, but...
Imagine you create a module of type M68000. It has a submodule of type BusAccess. To get a meaningful name in the rtlil and every tool that uses it, it is created in the recommended way in elaborate:
Then the name "busaccess" is used, which is good. But it seems that module names must be unique in the whole system. So does that mean one couldn't have two instances of M68000 in the same system if we want significant names?
The text was updated successfully, but these errors were encountered: