hdl.ir: Pick up the variable name as a default name for submodules #330
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The current generated rtlil uses name like U$$ for module names, which is not good for discoverability, implementing debuggers, etc. This patch picks up the variable name as default name for modules, in a similar way than is done for Signals.
I'm not sure what the rules for unicity are, if any. Maybe the name should include the hierarchy in it to avoid collisions. I'm not sure.