Add support for loading timing information in v2x from SDF #35
Description
We currently have a Python parser for loading SDF files. v2x is written in Python.
It would be good if for v2x we could use SDF files rather than timing attributes like found in the CARRY4_VPR module, see below;
(* whitebox *)
module CARRY4_VPR(O0, O1, O2, O3, CO_CHAIN, CO_FABRIC0, CO_FABRIC1, CO_FABRIC2, CO_FABRIC3, CYINIT, CIN, DI0, DI1, DI2, DI3, S0, S1, S2, S3);
parameter CYINIT_AX = 1'b0;
parameter CYINIT_C0 = 1'b0;
parameter CYINIT_C1 = 1'b0;
(* DELAY_CONST_CYINIT="0.491e-9" *)
(* DELAY_CONST_CIN="0.235e-9" *)
(* DELAY_CONST_S0="0.223e-9" *)
output wire O0;
(* DELAY_CONST_CYINIT="0.613e-9" *)
(* DELAY_CONST_CIN="0.348e-9" *)
(* DELAY_CONST_S0="0.400e-9" *)
(* DELAY_CONST_S1="0.205e-9" *)
(* DELAY_CONST_DI0="0.337e-9" *)
output wire O1;
(* DELAY_CONST_CYINIT="0.600e-9" *)
(* DELAY_CONST_CIN="0.256e-9" *)
(* DELAY_CONST_S0="0.523e-9" *)
(* DELAY_CONST_S1="0.558e-9" *)
(* DELAY_CONST_S2="0.226e-9" *)
(* DELAY_CONST_DI0="0.486e-9" *)
(* DELAY_CONST_DI1="0.471e-9" *)
output wire O2;Metadata
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mithro commentedon May 21, 2019
This should probably be done before f4pga/f4pga-arch-defs#748
mkurc-ant commentedon May 23, 2019
There is a PR: f4pga/f4pga-arch-defs#765
litghost commentedon Mar 2, 2020
This has been resolved by patching timing after arch is complete.
mithro commentedon Mar 5, 2020
@mkurc-ant Since you have been working on v2x related stuff recently, it could be worth taking another look at this issue and your original pull request at f4pga/f4pga-arch-defs#765 -- I'm pretty sure that atleast the test is probably worth transfering over.