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32-bit LUT-RAM are not correctly implemented #1269

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acomodi opened this issue Jan 17, 2020 · 2 comments
Open

32-bit LUT-RAM are not correctly implemented #1269

acomodi opened this issue Jan 17, 2020 · 2 comments
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arch-artix7 bug good first issue help wanted

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@acomodi
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acomodi commented Jan 17, 2020

Vendor tools dram tests were not enabled until #1234 got merged.

With #1268 I have temporarily disabled the vivado_targets, to let CI go green (as it has been red for too long now).

This issue is to keep track of the problem with DRAM evaluated on vendor tools with fasm2bels.
@acomodi acomodi mentioned this issue Jan 17, 2020
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@litghost litghost changed the title Vendor tools CI failing on DRAM tests 32-bit LUT-RAM are not correctly implemented Jan 23, 2020
@litghost
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litghost commented Jan 23, 2020 •
edited by acomodi

The current LUT-RAM implementation is likely wrong after #1267, but less wrong than before.

In particular:

  • RAM32X1S should be able to pack between 6-8 BELs in a SLICEM, currently only 4 are accomidated

For future work around this:

  • We need to consult the relevant documentation, and determine what are the valid packing schemes for 32-bit LUT-RAMs (using RAM32X1S, RAM32X1D and RAM32M).
  • Develop a set of Vivado mini-tests demonstrating the various packing options
  • Add those to symbiflow-arch-defs and verify that VPR can pack that tightly
  • Verify that fasm2bels can round trip those designs for analysis
  • Re-enable 32-bit LUT-RAM synthesis once previous steps are completed (e.g. enable inference for RAMB36E1 SymbiFlow/yosys#31)

@litghost litghost mentioned this issue Jan 23, 2020
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@litghost
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I've split the 32-bit LUT-RAM issues and 128/256 bit LUT-RAM issues into two seperate issues, with the 128/256 issues into #1275. This is because the fixes around the 128/256 is likely much less work than the fixes around the 32-bit LUT-RAM issues.

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