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Traceback (most recent call last):
File "repro.py", line 18, in <module>
print(rtlil.convert(Top()))
File "/home/jf/src/nmigen/nmigen/back/rtlil.py", line 1007, in convert
fragment = ir.Fragment.get(elaboratable, platform).prepare(**kwargs)
File "/home/jf/src/nmigen/nmigen/hdl/ir.py", line 67, in get
obj = obj.elaborate(platform)
File "/home/jf/src/nmigen/nmigen/hdl/dsl.py", line 484, in elaborate
fragment.add_subfragment(Fragment.get(self._named_submodules[name], platform), name)
File "/home/jf/src/nmigen/nmigen/hdl/ir.py", line 67, in get
obj = obj.elaborate(platform)
File "/home/jf/src/nmigen-soc/nmigen_soc/wishbone/bus.py", line 247, in elaborate
with m.Case(sub_pat[:-log2_int(self.bus.data_width // self.bus.granularity)]):
File "/usr/lib/python3.7/contextlib.py", line 112, in __enter__
return next(self.gen)
File "/home/jf/src/nmigen/nmigen/hdl/dsl.py", line 283, in Case
.format(pattern, len(switch_data["test"])))
nmigen.hdl.dsl.SyntaxError: Case pattern '' must have the same width as switch value (which is 5)
The text was updated successfully, but these errors were encountered:
Issue by jfng
Thursday Jan 23, 2020 at 11:44 GMT
Originally opened as m-labs/nmigen-soc#4
Repro:
Output:
The text was updated successfully, but these errors were encountered: