Records with zero-width fields used as module ports break Yosys #335

jfng · 2020-03-16T11:49:07Z

Repro:

from nmigen import *
from nmigen.back import rtlil, verilog


class Top(Elaboratable):
    def elaborate(self, platform):
        m = Module()

        r1 = Record([("addr", 0), ("data", 8)])
        r2 = Record([("addr", 0), ("data", 8)])
        r3 = Record([("addr", 0), ("data", 8)])

        m.submodules.a = a = Module()
        m.submodules.b = b = Module()

        a.d.comb += r1.eq(0)
        m.d.comb += r2.eq(r1)
        b.d.comb += r3.eq(r2)

        return m


print(verilog.convert(Top()))
# print(rtlil.convert(Top()))

This time Yosys chokes with a parser error:

Traceback (most recent call last):
  File "repro.py", line 23, in <module>
    print(verilog.convert(Top()))
  File "/home/jf/src/nmigen/nmigen/back/verilog.py", line 78, in convert
    return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs)
  File "/home/jf/src/nmigen/nmigen/back/verilog.py", line 66, in _convert_rtlil_text
    raise YosysError(error.strip())
nmigen.back.verilog.YosysError: ERROR: Parser error in line 37: syntax error

RTLIL output:

attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.a"
module \a
  attribute \src "repro.py:9"
  wire width 8 output 1 \r1__data
  wire width 1 $verilog_initial_trigger
  process $group_0
    assign { } 0'0
    assign \r1__data 8'00000000
    assign { \r1__data { } } 8'00000000
    assign $verilog_initial_trigger $verilog_initial_trigger
    sync init
      update $verilog_initial_trigger 1'0
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.b"
module \b
  attribute \src "repro.py:10"
  wire width 8 input 1 \r2__data
  attribute \src "repro.py:11"
  wire width 8 \r3__data
  process $group_0
    assign { } 0'0
    assign \r3__data 8'00000000
    assign { \r3__data { } } { \r2__data { } }
    sync init
  end
end
attribute \generator "nMigen"
attribute \top 1
attribute \nmigen.hierarchy "top"
module \top
  attribute \src "repro.py:9"
  wire width 8 \a_r1__data
  cell \a \a
    connect { } { }
    connect \r1__data \a_r1__data
  end
  attribute \src "repro.py:10"
  wire width 8 \b_r2__data
  cell \b \b
    connect { } { }
    connect \r2__data \b_r2__data
  end
  process $group_0
    assign { } 0'0
    assign \b_r2__data 8'00000000
    assign { \b_r2__data { } } { \a_r1__data { } }
    sync init
  end
end

Originally posted by @jfng in #312 (comment)

The text was updated successfully, but these errors were encountered:

whitequark added backend:rtlil bug labels Mar 16, 2020

whitequark added this to the 0.3 milestone Apr 13, 2020

whitequark closed this as completed in ee73d39 Apr 13, 2020

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Records with zero-width fields used as module ports break Yosys #335

Records with zero-width fields used as module ports break Yosys #335

jfng commented Mar 16, 2020

Records with zero-width fields used as module ports break Yosys #335

Records with zero-width fields used as module ports break Yosys #335

Comments

jfng commented Mar 16, 2020