Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: amaranth-lang/amaranth
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: ec3a21939e11
Choose a base ref
...
head repository: amaranth-lang/amaranth
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: b72c3fc7f697
Choose a head ref
  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Jan 31, 2020

  1. vendor.lattice_ecp5: support internal oscillator (OSCG).

    @miek @whitequark
    miek authored and whitequark committed Jan 31, 2020
    Copy the full SHA
    b72c3fc View commit details
Showing with 19 additions and 2 deletions.
  1. +19 −2 nmigen/vendor/lattice_ecp5.py
21 changes: 19 additions & 2 deletions nmigen/vendor/lattice_ecp5.py
View file
Original file line number Diff line number Diff line change
@@ -289,6 +289,12 @@ def command_templates(self):
return self._diamond_command_templates
assert False

@property
def default_clk_constraint(self):
if self.default_clk == "OSCG":
return Clock(310e6 / self.oscg_div)
return super().default_clk_constraint

def create_missing_domain(self, name):
# Lattice ECP5 devices have two global set/reset signals: PUR, which is driven at startup
# by the configuration logic and unconditionally resets every storage element, and GSR,
@@ -297,15 +303,26 @@ def create_missing_domain(self, name):
# network, its deassertion may violate a setup/hold constraint with relation to a user
# clock. To avoid this, a GSR/SGSR instance should be driven synchronized to user clock.
if name == "sync" and self.default_clk is not None:
clk_i = self.request(self.default_clk).i
m = Module()
if self.default_clk == "OSCG":
if not hasattr(self, "oscg_div"):
raise ValueError("OSCG divider (oscg_div) must be an integer between 2 "
"and 128")
if not isinstance(self.oscg_div, int) or self.oscg_div < 2 or self.oscg_div > 128:
raise ValueError("OSCG divider (oscg_div) must be an integer between 2 "
"and 128, not {!r}"
.format(self.oscg_div))
clk_i = Signal()
m.submodules += Instance("OSCG", p_DIV=self.oscg_div, o_OSC=clk_i)
else:
clk_i = self.request(self.default_clk).i
if self.default_rst is not None:
rst_i = self.request(self.default_rst).i
else:
rst_i = Const(0)

gsr0 = Signal()
gsr1 = Signal()
m = Module()
# There is no end-of-startup signal on ECP5, but PUR is released after IOB enable, so
# a simple reset synchronizer (with PUR as the asynchronous reset) does the job.
m.submodules += [