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base repository: amaranth-lang/amaranth
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base: b72c3fc7f697
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head repository: amaranth-lang/amaranth
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compare: 3ac13eb8f9a8
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Jan 31, 2020

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    3ac13eb View commit details
Showing with 3 additions and 0 deletions.
  1. +3 −0 nmigen/back/rtlil.py
3 changes: 3 additions & 0 deletions nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -278,6 +278,9 @@ def add_port(self, signal, kind):
self.ports[signal] = (len(self.ports), kind)

def resolve(self, signal, prefix=None):
if len(signal) == 0:
return "{ }", "{ }"

if signal in self.wires:
return self.wires[signal]