from nmigen import *

class MySubmodule(Elaboratable):
    def __init__(self, o):
        self.o = o

    def elaborate(self, platform):
        m = Module()
        m.d.comb += self.o.eq(1)
        return m

class Bug(Elaboratable):
    def elaborate(self, platform):
        m = Module()

        xo = Signal(2)
        m.submodules += [
            MySubmodule(xo[0]),
            MySubmodule(xo[1])
        ]

        return m

from nmigen.back import verilog
verilog.convert(Fragment.get(Bug(), None))