Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Branch : Quicklogic : In symbiflow, AssertionError reported #70

Closed
rakeshm75 opened this issue Apr 6, 2020 · 4 comments
Closed

Branch : Quicklogic : In symbiflow, AssertionError reported #70

rakeshm75 opened this issue Apr 6, 2020 · 4 comments

Comments

@rakeshm75
Copy link

In symbiflow, AssertionError reported:

make camif-ql-chandalar_jlink

Following error reported:
AssertionError: ('gpmc_ad(0)', 'FBIO_20')
make[3]: *** [quicklogic/tests/quicklogic_testsuite/camif/camif-ql-chandalar/ql-s3-ql-eos-s3-virt-ql-eos-s3-wlcsp/top_iomux.jlink] Error 1
make[3]: *** Deleting file `quicklogic/tests/quicklogic_testsuite/camif/camif-ql-chandalar/ql-s3-ql-eos-s3-virt-ql-eos-s3-wlcsp/top_iomux.jlink'
make[2]: *** [quicklogic/tests/quicklogic_testsuite/camif/CMakeFiles/camif-ql-chandalar_jlink.dir/all] Error 2
make[1]: *** [quicklogic/tests/quicklogic_testsuite/camif/CMakeFiles/camif-ql-chandalar_jlink.dir/rule] Error 2
make: *** [quicklogic/tests/quicklogic_testsuite/camif/CMakeFiles/camif-ql-chandalar_jlink.dir/rule] Error 2
rtl.zip

@kgugala
Copy link
Member

kgugala commented Apr 8, 2020

this is an assert in the jlink script generator. The bitstream itself is generated correctly. We'll take a look on the script

@kgugala
Copy link
Member

kgugala commented Apr 8, 2020

@rakeshm75 this is now fixed with antmicro/f4pga-arch-defs@c15f616

@tpagarani
Copy link

@kgugala , Thanks for providing this fix. While reviewing this script, we noticed that you are using the "mode" setting to set bit 5 and bit 11 on Pad config register. Actually for IOs used by FPGA, there is no need to set bit 5 and bit 11. They are only applicable when IO is not used by FPGA. In case of FPGA, OEN and REN are directly routed to FPGA interface. @rakeshm75 will send you a document to explain this. So you can skip setting these bits if ctrl_sel is Fabric.

@rakeshm75
Copy link
Author

This issue is resolved, so closing the issue.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

3 participants