Add support for iCE40 internal oscillators. #338
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…node IRC, who basically wrote this for me.
Codecov Report
@@ Coverage Diff @@
## master #338 +/- ##
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+ Coverage 82.54% 82.72% +0.18%
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Files 35 35
Lines 5924 5911 -13
Branches 1199 1199
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Hits 4890 4890
+ Misses 875 862 -13
Partials 159 159
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| if self.default_rst is not None: | ||
| rst_i = self.request(self.default_rst).i | ||
| else: | ||
| rst_i = Const(0) | ||
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| m = Module() | ||
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| # Power-on-reset domain | ||
| m.domains += ClockDomain("por", reset_less=True, local=True) | ||
| delay = int(15e-6 * self.default_clk_frequency) |
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Both SB_HFOSC and SB_LFOSC output is unstable for 100 µs after enabling them. So if one of these oscillators are selected, this power-on reset delay should be increased to 100 µs here.
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Huh, you learn something new every day. Should it have a 5x margin like the BRAM delay and be 500us, or is 100us okay?
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Nope, 100 us is OK. The reason BRAM delay has a 5x margin is that the 3 us figure is experimental (i.e. typical case) rather than provided by the vendor (i.e. worst case). Since we have no idea where that delay comes from it seems wise to play it safe, but that's not needed here.
…e default clock source.
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Okay, I think that should add a longer delay if an internal oscillator is selected. |
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Thanks for the PR! I've merged it with minor changes. |
Thanks to #nmigen on Freenode IRC; they basically wrote this for me.